Patents by Inventor Kazuo Kibi

Kazuo Kibi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11501998
    Abstract: There is formed, on a stack formed by alternately stacking an oxide film and a nitride film or an oxide film and a polysilicon film on a substrate, a hard mask in which two or more kinds of lines made of mutually different materials are arranged in order. Then, a photoresist is applied onto the hard mask. Furthermore, the photoresist is trimmed until one line is exposed from the end of the hard mask. Moreover, one line of the hard mask exposed beneath the photoresist is etched. Furthermore, a part of the stack exposed beneath the hard mask is etched. The etching of the photoresist, the hard mask, and the stack is repeated while changing etching conditions.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: November 15, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuo Kibi, Akihiro Takahashi, Wataru Sakamoto
  • Patent number: 11282753
    Abstract: In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 22, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Kazuo Kibi
  • Publication number: 20220013404
    Abstract: A method for example manufacturing a semiconductor device, which includes: forming a hole in a region of an insulating film laminated on a substrate; embedding a first conductive material in the hole to a position lower than a height of a sidewall of the hole; further embedding a second conductive material through a selective growth in the hole in which the first conductive material has been embedded; and etching the second conductive material to form a contact pad at a position above the hole.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Kazuo KIBI, Toshitake TSUDA, Kenji SUZUKI
  • Publication number: 20210384071
    Abstract: A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Kazuo KIBI, Shigetsugu FUJITA, Kenji SUZUKI, Mitsuhiro OKADA
  • Publication number: 20210082669
    Abstract: A plasma processing apparatus includes a process container that forms a process space to accommodate a target substrate, and a first electrode and a second electrode disposed opposite each other inside the process container. The first electrode is an upper electrode and the second electrode is a lower electrode and configured to support the target substrate through a mount face. A correction ring is disposed to surround the target substrate placed on the mount face of the second electrode. The correction ring includes a combination of a first ring to be around the target substrate and a second ring arranged around or above the first ring. A power supply unit is configured to apply a first electric potential and a second electric potential respectively to the first ring and the second ring to generate a potential difference between the first and second rings. The power supply unit is configured to variably set the potential difference.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Yoshinobu OHYA, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
  • Publication number: 20200381294
    Abstract: There is formed, on a stack formed by alternately stacking an oxide film and a nitride film or an oxide film and a polysilicon film on a substrate, a hard mask in which two or more kinds of lines made of mutually different materials are arranged in order. Then, a photoresist is applied onto the hard mask. Furthermore, the photoresist is trimmed until one line is exposed from the end of the hard mask. Moreover, one line of the hard mask exposed beneath the photoresist is etched. Furthermore, a part of the stack exposed beneath the hard mask is etched. The etching of the photoresist, the hard mask, and the stack is repeated while changing etching conditions.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Kazuo KIBI, Akihiro TAKAHASHI, Wataru SAKAMOTO
  • Patent number: 10854431
    Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Publication number: 20200365468
    Abstract: In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer.
    Type: Application
    Filed: January 21, 2019
    Publication date: November 19, 2020
    Applicant: Tokyo Electron Limited
    Inventor: Kazuo KIBI
  • Publication number: 20200111645
    Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Yoshinobu OHYA, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
  • Patent number: 10546727
    Abstract: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 28, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Patent number: 10529539
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Publication number: 20170032936
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
  • Publication number: 20160379805
    Abstract: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Publication number: 20160358753
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Applicant: Tokyo Electron Limited
    Inventors: Akira KOSHIISHI, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa
  • Patent number: 9490105
    Abstract: A plasma processing apparatus includes a first and second electrodes disposed on upper and lower sides and opposite each other within a process container, a first RF power application unit and a DC power supply both connected to the first electrode, and second and third radio frequency power application units both connected to the second electrode. A conductive member is disposed within the process container and grounded to release through plasma a current caused by a DC voltage applied from the DC power supply. The conductive member is supported by a first shield part around the second electrode and laterally protruding therefrom at a position between the mount face of the second electrode and an exhaust plate for the conductive member to be exposed to the plasma. The conductive member is grounded through a conductive internal body of the first shield part.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: November 8, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Publication number: 20140326409
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.
    Type: Application
    Filed: July 15, 2014
    Publication date: November 6, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Akira KOSHIISHI, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa
  • Patent number: 8790490
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 29, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa
  • Publication number: 20140124139
    Abstract: A plasma processing apparatus includes a first and second electrodes disposed on upper and lower sides and opposite each other within a process container, a first RF power application unit and a DC power supply both connected to the first electrode, and second and third radio frequency power application units both connected to the second electrode. A conductive member is disposed within the process container and grounded to release through plasma a current caused by a DC voltage applied from the DC power supply. The conductive member is supported by a first shield part around the second electrode and laterally protruding therefrom at a position between the mount face of the second electrode and an exhaust plate for the conductive member to be exposed to the plasma. The conductive member is grounded through a conductive internal body of the first shield part.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 8, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Yoshinobu OHYA, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
  • Patent number: 8603293
    Abstract: A plasma processing apparatus includes a processing container, an exhaust unit, an exhaust plate, an RF power application unit connected to a second electrode but not connected to the first electrode and configured to apply an RF power with a single frequency, the second electrode being connected to no power supply that applies an RF power other than the RF power with the single frequency, a DC power supply connected to the first electrode but not connected to the second electrode, the first electrode being connected to no power supply that applies an RF power, and a conductive member within the process container grounded to release through plasma a current caused by the DC voltage, the conductive member supported by the first shield part and laterally protruding therefrom only at a position that is located, in a height-wise direction, between a mount face and the exhaust plate and below a bottom of a focus ring.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: December 10, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Publication number: 20120145324
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.
    Type: Application
    Filed: February 14, 2012
    Publication date: June 14, 2012
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa