Abstract: A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.

Abstract: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.

Abstract: An object of the present invention is to provide a composition for the formation of a cured epoxy resin, wherein the composition can suppress a curing reaction at a low temperature to thereby enhance one-pack stability, and can also be subjected to a heating treatment to thereby effectively cure a resin. The present invention provides a composition for the formation of a cured epoxy resin, the composition comprising the following components (A), (B) and (C): (A) an epoxy resin; (B) a clathrate compound of a carboxylic acid derivative represented by formula (I): R(COOH)n??(I); and an imidazole compound represented by formula (II); and (C) a tetrakisphenol type compound represented by formula (III).

Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

Abstract: It is an object of the present invention to provide a clathrate that suppresses a curing reaction at low temperature to promote an improvement in storage stability (one-component stability), and can effectively cure a resin by heating treatment. A clathrate suitable for the clathrate is a clathrate containing (b1) at least one selected from the group consisting of an aliphatic polyvalent carboxylic acid, 5-nitroisophthalic acid, 5-tert-butylisophthalic acid, 5-hydroxyisophthalic acid, isophthalic acid, and benzophenone-4,4?-dicarboxylic acid; and (b2) at least one selected from the group consisting of an imidazole compound represented by the following formula (I), and 1,8-diazabicyclo[5.4.0]undecene-7, at a molar ratio of 1:1.

Abstract: A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.

Abstract: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.

Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

Abstract: A microphone capable of canceling vibration noise caused by mechanical vibration is provided with, in capsules, a pair of diaphragms and a pair of back plates opposite to the respective diaphragms. A printed circuit board is disposed at the middle of capsules. A pair of diaphragms is disposed close and opposite to the surfaces of the printed circuit board with the printed circuit board disposed therebetween. The difference in distance from a vibration source to the two diaphragms is made small. The microphone has a high canceling effect for canceling vibration noise caused by mechanical vibration.

Abstract: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.

Abstract: A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect element 101 of the magnetic memory cell, a mechanism 601-604 for dropping the threshold magnetization switching current on “1” writing is provided that applies a magnetic field that is in the inverse direction of the pinned layer to the recording layer of the magnetoresistance effect element.

Abstract: A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.

Abstract: Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. 1).

Abstract: A unidirectional microphone includes a cylindrical capsule, a front plate blocking one end of the cylindrical capsule, a front plate sound hole formed in the front plate, a vibrating membrane and a first rear pole plate that are housed in the cylindrical capsule and form capacitance, a substrate blocking another open end of the capsule, and a rear plate sound hole formed in the substrate. The front plate sound hole and the rear plate sound hole are placed on mutually opposite sides of a central axis of the capsule so as to be offset relative to the central axis. The directional axis can be significantly offset relative to the central axis of the microphone using the microphone alone.

Abstract: A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.

Abstract: The invention is an epoxy resin composition for sealing a semiconductor, including (A) an epoxy resin and (B) a clathrate complex. The clathrate complex is one of (b1) an aromatic carboxylic acid compound, and (b2) at least one imidazole compound represented by formula (II): wherein R2 represents a hydrogen atom, C1-C10 alkyl group, phenyl group, benzyl group or cyanoethyl group, and R3 to R5 represent a hydrogen atom, nitro group, halogen atom, C1-C20 alkyl group, phenyl group, benzyl group, hydroxymethyl group or C1-C20 acyl group. The composition has improved storage stability, retains flowability when sealing, and achieves an effective curing rate applicable for sealing delicate semiconductors.

Abstract: A solid semiconductor sealing composition that includes (A) an epoxy resin, and (B) a clathrate complex. The clathrate complex contains (b1) at least one of 5-hydroxyisophthalic acid and 5-nitroisophthalic acid; and (b2) at least one of 2-ethyl-4-methylimidazole and 2-phenyl-4-methyl-5-hydroxymethylimidazole. A method of sealing a solid semiconductor using the sealing composition.

Abstract: The present invention provides a liquid curable epoxy resin composition that has excellent storage stability and curing properties and provides a cured product having excellent properties, particularly, excellent organic solvent resistance. For that purpose, a clathrate containing a carboxylic acid compound and at least one selected from the group consisting of an imidazole compound represented by formula (I), wherein R1 to R4 each represent a hydrogen atom or the like, and 1,8-diazabicyclo[5.4.0]undecene-7 (DBU) is mixed in an epoxy resin. The liquid curable epoxy resin composition uses a liquid epoxy resin or an organic solvent.

Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.