Patents by Inventor Kazuo Otsuga
Kazuo Otsuga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150220095Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: Masafumi ONOUCHI, Kazuo OTSUGA, Yasuto IGARASHI, Sadayuki MORITA, Koichiro ISHIBASHI, Kazumasa YANAGISAWA
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Patent number: 9030176Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: GrantFiled: November 12, 2012Date of Patent: May 12, 2015Assignee: Renesas Electronics CorporationInventors: Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa
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Publication number: 20150046729Abstract: First and second processing units execute a binary program. A temperature sensor measures a temperature of a first processing unit. A temperature detection unit outputs a first interrupt instruction when the temperature measured by the temperature sensor exceeds a first value. A bus exchanges data between the first and second processing units. In response to the first interrupt instruction, the control unit interrupts execution in the first processing unit, migrates first data that is necessary for resuming the execution of the binary program from the first processing unit to the second processing unit, and controls the second processing unit to resume the execution of the binary program in the second processing unit. A power control unit interrupts power supply to the first processing unit after the first data is migrated to the second processing unit.Type: ApplicationFiled: August 7, 2014Publication date: February 12, 2015Inventors: Kazuki FUKUOKA, Kazuo OTSUGA
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Patent number: 8339190Abstract: AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.Type: GrantFiled: January 25, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Kazuo Otsuga, Yusuke Kanno, Yoshio Takazawa
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Patent number: 8248099Abstract: In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor.Type: GrantFiled: May 25, 2010Date of Patent: August 21, 2012Assignee: Renesas Electronics CorporationInventors: Kazuo Otsuga, Yusuke Kanno
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Patent number: 8030956Abstract: A semiconductor integrated circuit that includes a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.Type: GrantFiled: September 9, 2010Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Kazuo Otsuga, Tetsuya Yamada, Kenichi Osada, Yusuke Kanno
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Patent number: 7994822Abstract: The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.Type: GrantFiled: January 20, 2010Date of Patent: August 9, 2011Assignee: Hitachi, Ltd.Inventors: Kazuo Otsuga, Kenichi Osada, Makoto Saen
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Publication number: 20110181337Abstract: AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.Type: ApplicationFiled: January 25, 2011Publication date: July 28, 2011Inventors: KAZUO OTSUGA, Yusuke Kanno, Yoshio Takazawa
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Patent number: 7954023Abstract: A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.Type: GrantFiled: December 22, 2008Date of Patent: May 31, 2011Assignee: Renesas Electronics CorporationInventors: Kazuo Otsuga, Kenichi Osada, Yusuke Kanno
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Publication number: 20110006792Abstract: A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.Type: ApplicationFiled: September 9, 2010Publication date: January 13, 2011Inventors: Kazuo Otsuga, Tetsuya Yamada, Kenichi Osada, Yusuke Kanno
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Publication number: 20100301893Abstract: In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor.Type: ApplicationFiled: May 25, 2010Publication date: December 2, 2010Inventors: Kazuo OTSUGA, Yusuke Kanno
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Patent number: 7812628Abstract: A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.Type: GrantFiled: December 13, 2007Date of Patent: October 12, 2010Assignee: Renesas Electronics CorporationInventors: Kazuo Otsuga, Tetsuya Yamada, Kenichi Osada, Yusuke Kanno
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Publication number: 20100182046Abstract: The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.Type: ApplicationFiled: January 20, 2010Publication date: July 22, 2010Inventors: Kazuo Otsuga, Kenichi Osada, Makoto Saen
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Publication number: 20090160544Abstract: A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.Type: ApplicationFiled: December 22, 2008Publication date: June 25, 2009Inventors: Kazuo Otsuga, Kenichi Osada, Yusuke Kanno
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Publication number: 20090024810Abstract: In a storage device, a method is provided for preventing the risk of data loss and a significant decrease of writing speed due to area shrinkage when erased erase blocks have become fewer. A process of allocating a new page includes determining whether the length of a deallocated pages list is longer than n pages. If the list length is longer, one page is allocated from the deallocated pages list. If the list length is shorter, a capacity shortage error returns. Deleting a file using an erased pages list includes determining whether a page to be processed is emptied by deleting the file. If not so, the file is deleted from the page. If so, the contents of the last page-a in occupied pages are copied to the page, the page-a is written with data for erasure, and any erase block included in the page-a is made erasable.Type: ApplicationFiled: July 15, 2008Publication date: January 22, 2009Inventors: Daisuke Ito, Shinji Fujiwara, Kazuo Otsuga, Shinya Kajiyama
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Patent number: 7471563Abstract: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.Type: GrantFiled: January 11, 2007Date of Patent: December 30, 2008Assignee: Renesas Technology Corp.Inventors: Hideaki Kurata, Kazuo Otsuga, Yoshitaka Sasago, Takashi Kobayashi, Tsuyoshi Arigane
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Publication number: 20080143184Abstract: A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.Type: ApplicationFiled: December 13, 2007Publication date: June 19, 2008Inventors: Kazuo OTSUGA, Tetsuya Yamada, Kenichi Osada, Yusuke Kanno
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Patent number: 7323741Abstract: A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.Type: GrantFiled: November 30, 2004Date of Patent: January 29, 2008Assignee: Renesas Technology Corp.Inventors: Kazuo Otsuga, Hideaki Kurata, Yoshitaka Sasago
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Publication number: 20070109870Abstract: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.Type: ApplicationFiled: January 11, 2007Publication date: May 17, 2007Inventors: Hideaki Kurata, Kazuo Otsuga, Yoshitaka Sasago, Takashi Kobayashi, Tsuyoshi Arigane
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Patent number: 7184318Abstract: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.Type: GrantFiled: August 5, 2005Date of Patent: February 27, 2007Assignee: Renesas Technology Corp.Inventors: Hideaki Kurata, Kazuo Otsuga, Yoshitaka Sasago, Takashi Kobayashi, Tsuyoshi Arigane