Patents by Inventor Kazuo Sakamoto

Kazuo Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210301143
    Abstract: Provided is a surface-treated spinel particle (B) including a spinel particle (A) including a magnesium atom, an aluminum atom, and an oxygen atom and a surface treatment layer disposed at least a portion of the surface of the spinel particle (A). The surface treatment layer includes a surface-treating agent including an organic compound or a cured product of the surface-treating agent. The spinel particle (A) further includes molybdenum. The crystallite diameter of the [111] plane of the spinel particle (A) is 220 nm or more. Also provided are a method for producing the surface-treated spinel particle (B), a resin composition including the surface-treated spinel particle (B), and a molded article.
    Type: Application
    Filed: September 21, 2017
    Publication date: September 30, 2021
    Applicant: DIC Corporation
    Inventors: Kazuo Itoya, Atsushi Oshio, Hironobu Oki, Masaki Iida, Yasuyo Sakamoto, Masamichi Hayashi, Takayuki Kanematsu, Fumihiko Maekawa, Jian-Jun Yuan, Hiroshi Kinoshita
  • Publication number: 20210290129
    Abstract: A state of a user of a mobile terminal having a display for displaying an image may be estimated. A sightline detection detector detects a user's sightline of a mobile terminal that has a display for displaying an image. Processing circuitry is configured to estimate a state of the user including an attention function degraded state based on motion of the user's sightline with respect to the image displayed on the display of the mobile terminal.
    Type: Application
    Filed: February 18, 2021
    Publication date: September 23, 2021
    Applicant: Mazda Motor Corporation
    Inventors: Koji IWASE, Kazuo SAKAMOTO, Akihide TAKAMI
  • Publication number: 20210290128
    Abstract: A state of a user of a mobile terminal having a display for displaying an image maybe estimated. A sightline detector detects a sightline of the user of a mobile terminal and processing circuitry is configured to estimate a state of the user. The processing circuitry is configured to determine a top-down index value that is correlated with an attention source amount allocated to top-down attention of the user with respect to an image displayed on a display of the mobile terminal. The processing circuitry is configured to determine a bottom-up index value correlated with the attention source amount allocated to bottom-up attention of the user with respect to the image displayed on the display. The processing circuitry is configured to estimate the user state including an attention function degraded state based on the top-down index value and the bottom-up index value.
    Type: Application
    Filed: February 18, 2021
    Publication date: September 23, 2021
    Applicant: Mazda Motor Corporation
    Inventors: Koji IWASE, Kazuo SAKAMOTO, Akihide TAKAMI
  • Patent number: 10396080
    Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuo Sakamoto, Toshiaki Ito
  • Publication number: 20190006364
    Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.
    Type: Application
    Filed: May 21, 2018
    Publication date: January 3, 2019
    Inventors: Kazuo SAKAMOTO, Toshiaki ITO
  • Patent number: 9868666
    Abstract: The cement clinker production system includes: a first supplying section configured to supply a sulfur source and a fluorine source of mineralizer; a second supplying device configured to supply clinker raw material; a crusher configured to crush the mixed raw material obtained by mixing the clinker raw material with the fluorine source of the mineralizer; a kiln configured to burn the crushed mixed raw material; an introducing section configured to introduce the sulfur source of the mineralizer to the kiln; a third supplying section configured to supply fuel to the kiln; and a test sample-analyzing system configured to collect each of the mixed raw material before the burning and the clinker after the burning and to measure amounts of the fluorine, main components and free lime depending on the type collected.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: January 16, 2018
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Makio Yamashita, Hisanobu Tanaka, Yukio Tanaka, Katsuhiko Ichihara, Kazuo Sakamoto, Kazuo Tabata
  • Patent number: 9515019
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20160271394
    Abstract: The purpose of the present invention is, when treating circulatory disease such as acute myocardial infarction, to correct a reduction in myocardial contractility and thereby prevent arrhythmia and the like, as well as to reduce infarct size. Provided is a neurostimulation device having a stimulus application part configured so as to apply a stimulus to a cervical or thoracic vagus nerve portion in a human or an animal, and a stimulus regulation part configured so as to regulate the quantity of stimulus applied from the stimulus application part to the vagus nerve portion. The stimulus regulation part establishes a quantity of stimulus that is less than a value at which adverse effects would be produced, determines the heart rate and R wave interval of the human or animal, and controls the quantity of stimulus on the basis of these determinations.
    Type: Application
    Filed: October 20, 2014
    Publication date: September 22, 2016
    Inventors: Kenji SUNAGAWA, Tomomi IDE, Kazuo SAKAMOTO
  • Publication number: 20160233154
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: April 14, 2016
    Publication date: August 11, 2016
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Patent number: 9379100
    Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.
    Type: Grant
    Filed: November 28, 2015
    Date of Patent: June 28, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
  • Patent number: 9343460
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 17, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20160079231
    Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.
    Type: Application
    Filed: November 28, 2015
    Publication date: March 17, 2016
    Inventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
  • Patent number: 9209811
    Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: December 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
  • Publication number: 20150287724
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150246849
    Abstract: The cement clinker production system includes: a first supplying section configured to supply a sulfur source and a fluorine source of mineralizer; a second supplying device configured to supply clinker raw material; a crusher configured to crush the mixed raw material obtained by mixing the clinker raw material with the fluorine source of the mineralizer; a kiln configured to burn the crushed mixed raw material; an introducing section configured to introduce the sulfur source of the mineralizer to the kiln; a third supplying section configured to supply fuel to the kiln; and a test sample-analyzing system configured to collect each of the mixed raw material before the burning and the clinker after the burning and to measure amounts of the fluorine, main components and free lime depending on the type collected.
    Type: Application
    Filed: December 20, 2012
    Publication date: September 3, 2015
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Makio Yamashita, Hisanobu Tanaka, Yukio Tanaka, Katsuhiko Ichihara, Kazuo Sakamoto, Kazuo Tabata
  • Patent number: 9093283
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 28, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150108579
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 23, 2015
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20150108001
    Abstract: Disclosed is a liquid processing jig for performing a predetermined processing on a workpiece using a processing liquid. The liquid processing jig includes: a liquid processing unit formed on a surface of the liquid processing jig and configured to perform a predetermined processing on the workpiece by the processing liquid; a liquid supplying unit configured to supply the processing liquid to the liquid processing unit; a liquid supplying channel configured to connect the liquid supplying unit and the liquid processing unit and supply the processing liquid from the liquid supplying unit to the liquid processing unit; and a liquid discharging channel configured to discharge the processing liquid from the liquid processing unit. The liquid supplying unit, the liquid supplying channel, the liquid processing unit, and the liquid discharging channel are provided to cause the processing liquid to flow by a capillary phenomenon.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kazuo SAKAMOTO, Haruo IWATSU
  • Patent number: 8946770
    Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
  • Publication number: 20140354331
    Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Inventors: Kazuo SAKAMOTO, Naozumi MORINO, Kazuo TANAKA, Hiroyasu ISHIZUKA