Patents by Inventor Kazuo Sakamoto
Kazuo Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140354331Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: ApplicationFiled: August 15, 2014Publication date: December 4, 2014Inventors: Kazuo SAKAMOTO, Naozumi MORINO, Kazuo TANAKA, Hiroyasu ISHIZUKA
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Publication number: 20140311530Abstract: A substrate processing method of performing a predetermined processing by supplying a processing liquid to a processing region on a surface of a substrate, includes: supplying an alignment liquid to an alignment region on the surface of the substrate formed at a position different from that of the processing region; aligning a template disposed facing the substrate and including a processing liquid passage configured to pass the processing liquid and an alignment liquid passage configured to pass the alignment liquid, with respect to the substrate with the alignment liquid supplied to the alignment region such that the processing liquid passage is positioned above the processing region; and performing the predetermined processing on the substrate by supplying the processing liquid to the processing region through the processing liquid passage.Type: ApplicationFiled: October 22, 2012Publication date: October 23, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Haruo Iwatsu, Takayuki Toshima, Kazuo Sakamoto
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Patent number: 8813678Abstract: A substrate processing apparatus including a holder for rotatably holding a substrate; a coating solution supply nozzle for supplying a coating solution onto a front surface of the substrate to be processed held by the holder; a treatment chamber housing the holder and the coating solution supply nozzle; a cooling device which cools the substrate before the coating solution is supplied to the substrate, to a predetermined temperature; a heating devices which heats the substrate coated with the coating solution to a predetermined temperature; and a transferer that transfers the substrate between the treatment chamber, the cooling device and the heating device, wherein the treatment chamber, the cooling device and the heating device are partitioned from ambient air, and wherein at least the treatment chamber is connected to a gas supply mechanism having a supply source of a gas having a kinematic viscosity coefficient higher than that of air.Type: GrantFiled: August 15, 2012Date of Patent: August 26, 2014Assignee: Tokyo Electron LimitedInventor: Kazuo Sakamoto
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Patent number: 8810278Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: October 18, 2012Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20130341728Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Applicant: Renesas Electronics CorporationInventors: Takahiro HAYASHI, Shunsuke TOYOSHIMA, Kazuo SAKAMOTO, Naozumi MORINO, Kazuo TANAKA
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Patent number: 8572425Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: July 19, 2012Date of Patent: October 29, 2013Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
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Patent number: 8552561Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: GrantFiled: March 19, 2010Date of Patent: October 8, 2013Assignee: Renesas Electronics CorporationInventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Patent number: 8345514Abstract: A radio-controlled timepiece in which its reception sensitivity is further enhanced. The radio-controlled timepiece includes: an antenna core 11 made of a magnetic material and formed as a single integrated body including a coiled portion (11a) wound with a coil 19 and extension portions 11b and 11c which are located respectively on the end-portion sides; additional cores 15 and 16 made of a magnetic material; magnetism-collection members 17 and 18 made of a magnetic material; a main plate 31 (timepiece substrate) made of a non-magnetic material; a guide member 33 made of a non-magnetic material; and a liquid-crystal-panel supporting frame 32 (magnetism-collection-member supporting members, pressing member) made of a non-magnetic material and having protrusions 32a and 32b (pressing members) formed thereon. When the main plate 31, the guide member 33, and the liquid-crystal-panel supporting frame 32 are assembled together, the protrusions 32a and 32b press the magnetism-collection members, respectively.Type: GrantFiled: March 5, 2008Date of Patent: January 1, 2013Assignee: Citizen Holdings Co., Ltd.Inventors: Tatsuo Sumida, Kazuo Sakamoto, Tadashi Yasuoka
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Publication number: 20120304920Abstract: A substrate processing apparatus including a holder for rotatably holding a substrate; a coating solution supply nozzle for supplying a coating solution onto a front surface of the substrate to be processed held by the holder; a treatment chamber housing the holder and the coating solution supply nozzle; a cooling device which cools the substrate before the coating solution is supplied to the substrate, to a predetermined temperature; a heating devices which heats the substrate coated with the coating solution to a predetermined temperature; and a transferer that transfers the substrate between the treatment chamber, the cooling device and the heating device, wherein the treatment chamber, the cooling device and the heating device are partitioned from ambient air, and wherein at least the treatment chamber is connected to a gas supply mechanism having a supply source of a gas having a kinematic viscosity coefficient higher than that of air.Type: ApplicationFiled: August 15, 2012Publication date: December 6, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Kazuo SAKAMOTO
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Patent number: 8327180Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: June 3, 2011Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
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Publication number: 20120284554Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Inventors: KAZUO SAKAMOTO, Naozumi MORINO, Ikuo KUDO
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Patent number: 8267037Abstract: A substrate processing apparatus including a holder for rotatably holding a substrate; a coating solution supply nozzle for supplying a coating solution onto a front surface of the substrate to be processed held by the holder; a treatment chamber housing the holder and the coating solution supply nozzle; a cooling device which cools the substrate before the coating solution is supplied to the substrate, to a predetermined temperature; a heating devices which heats the substrate coated with the coating solution to a predetermined temperature; and a transferer that transfers the substrate between the treatment chamber, the cooling device and the heating device, wherein the treatment chamber, the cooling device and the heating device are partitioned from ambient air, and wherein at least the treatment chamber is connected to a gas supply mechanism having a supply source of a gas having a kinematic viscosity coefficient higher than that of air.Type: GrantFiled: July 2, 2008Date of Patent: September 18, 2012Assignee: Tokyo Electron LimitedInventor: Kazuo Sakamoto
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Publication number: 20110231694Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Inventors: KAZUO SAKAMOTO, Naozumi Morino, Ikuo Kudo
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Patent number: 8006636Abstract: A substrate treatment apparatus of the present invention includes: a holding means for rotatably holding a substrate to be treated; a coating solution supply nozzle for supplying a coating solution onto the front surface of the substrate to be treated held on the holding means; a treatment container with an upper surface open for housing them; an exhaust means for exhausting an atmosphere in the treatment container from the bottom; a multiblade centrifugal fan provided on the inner periphery of the treatment container for flowing airflow on a front surface side of the substrate to the exhaust means; and a controller for controlling the number of rotations of the multiblade centrifugal fan corresponding to the number of rotations of the substrate, wherein the number of rotations of the multiblade centrifugal fan is controlled so that turbulent airflow flowing in a circumferential direction on the front surface of the substrate generated due to the rotation of the substrate is corrected to laminar airflow flowiType: GrantFiled: July 22, 2008Date of Patent: August 30, 2011Assignee: Tokyo Electron LimitedInventors: Kazuo Terada, Kazuo Sakamoto, Takeshi Uehara
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Patent number: 7966512Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: January 4, 2009Date of Patent: June 21, 2011Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
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Patent number: 7821877Abstract: A pointer indication type timepiece, wherein three projecting portions (11) projecting from a shaft part (112) to an outer peripheral side and formed in such a shape that a cylinder is split into two parts along a central axis direction are disposed at a root portion (113) of the shaft part (112) of an hour wheel (110) at equal intervals in the circumferential direction of the shaft part (112). The projecting portions (11) engage with a circular hole (123) in a dial washer (120).Type: GrantFiled: February 21, 2006Date of Patent: October 26, 2010Assignee: Citizen Holdings Co., Ltd.Inventors: Shin-ichi Sakamaki, Kazuo Sakamoto, Masanori Katayama
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Publication number: 20100171177Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: ApplicationFiled: March 19, 2010Publication date: July 8, 2010Inventors: Takahiro HAYASHI, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Patent number: 7714357Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: GrantFiled: October 17, 2008Date of Patent: May 11, 2010Assignee: Renesas Technology Corp.Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Publication number: 20100097895Abstract: A radio-controlled timepiece in which its reception sensitivity is further enhanced. The radio-controlled timepiece includes: an antenna core 11 made of a magnetic material and formed as a single integrated body including a coiled portion (11a) wound with a coil 19 and extension portions 11b and 11c which are located respectively on the end-portion sides; additional cores 15 and 16 made of a magnetic material; magnetism-collection members 17 and 18 made of a magnetic material; a main plate 31 (timepiece substrate) made of a non-magnetic material; a guide member 33 made of a non-magnetic material; and a liquid-crystal-panel supporting frame 32 (magnetism-collection-member supporting members, pressing member) made of a non-magnetic material and having protrusions 32a and 32b (pressing members) formed thereon. When the main plate 31, the guide member 33, and the liquid-crystal-panel supporting frame 32 are assembled together, the protrusions 32a and 32b press the magnetism-collection members, respectively.Type: ApplicationFiled: March 5, 2008Publication date: April 22, 2010Inventors: Tatsuo Sumida, Kazuo Sakamoto, Tadashi Yasuoka
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Patent number: 7579882Abstract: A novel output buffer circuit including an input circuit, a voltage generating circuit, and an output circuit forms a three-state buffer circuit. The output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. With such a configuration, a simple circuit using no high voltage insulated transistors and level shift circuits can be made, and the simple circuit can output either a low voltage signal or a high voltage signal responsive to a low voltage input signal, reduce the manufacturing cost and the delay of the risetime of the output signal, which are associated with a high voltage insulated transistor. Furthermore, cost can be reduced by miniaturization of the circuit size.Type: GrantFiled: March 2, 2006Date of Patent: August 25, 2009Assignee: Ricoh Company, Ltd.Inventors: Kazuo Sakamoto, Yasunori Nakayama