Patents by Inventor Kazuo Tomita
Kazuo Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110012224Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: ApplicationFiled: September 27, 2010Publication date: January 20, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kazuo TOMITA
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Publication number: 20110012225Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: ApplicationFiled: September 27, 2010Publication date: January 20, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kazuo TOMITA
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Publication number: 20110001242Abstract: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.Type: ApplicationFiled: September 17, 2010Publication date: January 6, 2011Applicant: Renesas Technology CorporationInventor: Kazuo TOMITA
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Patent number: 7843066Abstract: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.Type: GrantFiled: August 3, 2009Date of Patent: November 30, 2010Assignee: Renesas Technologies CorporationInventor: Kazuo Tomita
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Patent number: 7825489Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: GrantFiled: November 5, 2008Date of Patent: November 2, 2010Assignee: Renesas Electronics CorporationInventor: Kazuo Tomita
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Patent number: 7719078Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: GrantFiled: November 5, 2008Date of Patent: May 18, 2010Assignee: Renesas Technology Corp.Inventor: Kazuo Tomita
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Publication number: 20090289373Abstract: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.Type: ApplicationFiled: August 3, 2009Publication date: November 26, 2009Applicant: Renesas Technology Corp.Inventor: Kazuo Tomita
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Patent number: 7605085Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.Type: GrantFiled: September 18, 2006Date of Patent: October 20, 2009Assignees: Renesas Technology Corp., Panasonic CorporationInventors: Kazuo Tomita, Keiji Hashimoto, Yasutaka Nishioka, Susumu Matsumoto, Mitsuru Sekiguchi, Akihisa Iwasaki
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Patent number: 7550815Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: GrantFiled: August 9, 2007Date of Patent: June 23, 2009Assignee: Renesas Technology Corp.Inventor: Kazuo Tomita
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Publication number: 20090072345Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: ApplicationFiled: November 5, 2008Publication date: March 19, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventor: Kazuo TOMITA
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Publication number: 20090072346Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: ApplicationFiled: November 5, 2008Publication date: March 19, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventor: Kazuo TOMITA
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Publication number: 20090032847Abstract: A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench isolation film; a contact interlayer film; and a multilayer interconnection structure formed by alternate laminations of low-k via interlayer films, i.e., V layers, and low-k interconnect interlayer films, i.e., M layers. In a Fine layer ranging from first to fifth interlayer films, the M layers are removed from the wafer edge portion, but the V layers are not removed therefrom. Further, the contact interlayer film is not removed from the wafer edge portion.Type: ApplicationFiled: July 31, 2008Publication date: February 5, 2009Inventor: Kazuo Tomita
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Publication number: 20080315366Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an a interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.Type: ApplicationFiled: April 22, 2008Publication date: December 25, 2008Applicant: Renesas Technology Corp.Inventor: Kazuo TOMITA
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Publication number: 20080296777Abstract: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.Type: ApplicationFiled: August 6, 2008Publication date: December 4, 2008Applicant: Renesas Technology Corp.Inventor: Kazuo TOMITA
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Publication number: 20080283961Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: ApplicationFiled: August 9, 2007Publication date: November 20, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventor: Kazuo Tomita
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Patent number: 7420278Abstract: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part.Type: GrantFiled: June 20, 2006Date of Patent: September 2, 2008Assignee: Renesas Technology Corp.Inventor: Kazuo Tomita
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Patent number: 7400028Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.Type: GrantFiled: June 17, 2005Date of Patent: July 15, 2008Assignee: Renesas Technology Corp.Inventor: Kazuo Tomita
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Patent number: 7304365Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.Type: GrantFiled: May 24, 2005Date of Patent: December 4, 2007Assignee: Renesas Technology Corp.Inventor: Kazuo Tomita
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Patent number: 7225659Abstract: A punch press tool includes a cylindrical punch guide in which a punch body provided with a punch tip for press forming is fit slidably. The punch tip consists of an appropriate number of long forming punch tips each including a press forming portion in the leading end thereof. The punch tip also consists of an appropriate number of clamping punch tips each with a shorter length compared with the forming punch tips. Both of the tips are attached to the punch body detachably and exchangeably.Type: GrantFiled: June 12, 2003Date of Patent: June 5, 2007Assignee: Amada Company, LimitedInventor: Kazuo Tomita
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Publication number: 20070007658Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.Type: ApplicationFiled: September 18, 2006Publication date: January 11, 2007Applicants: RENESAS TECHNOLOGY CORP., MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuo TOMITA, Keiji HASHIMOTO, Yasutaka NISHIOKA, Susumu MATSUMOTO, Mitsuru SEKIGUCHI, Akihisa IWASAKI