Patents by Inventor Kazuo Tomita

Kazuo Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020197819
    Abstract: An element isolation trench is formed in a mark section of a substrate. Further, an element isolation dielectric film is formed in the element isolation trench. An etch stopper film formed from a silicon nitride film is formed so as to cover at least a portion of the surface of an element isolation dielectric film formed in the mark section. Circuit elements are formed in a circuit section of the substrate while the etch stopper film formed in the mark section is used as an inspection mark.
    Type: Application
    Filed: April 10, 2002
    Publication date: December 26, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Publication number: 20020100978
    Abstract: A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 1, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kazuo Tomita, Atsushi Ueno
  • Publication number: 20020093040
    Abstract: Disclosed herein is a semiconductor device wherein element active regions for an N channel region and a P channel region are formed so as to adjoin each other, and gate electrode is formed so as to stride over both channel regions and an element isolation oxide film for separating both channel regions from each other. In the semiconductor device, the gate electrode comprises a structure wherein a polycrystalline silicon film, a first barrier metal film, a second barrier metal film and a metal film are laminated in order from below. The first barrier metal film is removed at the border part between the N channel region and the P channel region.
    Type: Application
    Filed: July 24, 2001
    Publication date: July 18, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Patent number: 6376924
    Abstract: A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: April 23, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuo Tomita, Atsushi Ueno
  • Patent number: 6344406
    Abstract: It is possible to obtain a semiconductor device in which a contact and a wiring provided on the contact can be electrically connected well even if a shift of superposition is caused. Sidewalls 5a, 5b, 5c and 5d formed of a conductive material directly making contact with side faces of wirings 4a and 4b to be provided on contacts 3a and 3b. Consequently, the wirings 4a and 4b and the contacts 3a and 3b can be electrically connected well through the sidewalls 5a, 5b, 5c and 5d.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: February 5, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Publication number: 20020008573
    Abstract: A demodulation apparatus of the present invention comprises: an A/D converter for sampling and quantizing a baseband signal; a transversal filter having time-shifted tap coefficients; a decision unit for decoding the signal which has undergone the transversal filter; and a decision point estimation unit for instructing the transversal filter to select the tap coefficient to be selected based on information from the decision unit. Thus, the demodulation apparatus can operate at the same frequency as a sampling frequency of the A/D converter and can perform decision with accuracy equivalent to an arbitrary oversampling number.
    Type: Application
    Filed: May 9, 2001
    Publication date: January 24, 2002
    Inventors: Yoshinori Kunieda, Kazuo Tomita, Hidekuni Yomo
  • Publication number: 20010023122
    Abstract: It is possible to obtain a semiconductor device in which a contact and a wiring provided on the contact can be electrically connected well even if a shift of superposition is caused. Sidewalls 5a, 5b, 5c and 5d formed of a conductive material are bonded to side faces of wirings 4a and 4b to lee provided on contacts 3a and 3b. Consequently, the wirings 4a and 4b and the contacts 3a and 3b can be electrically connected well through the sidewalls 5a, 5b, 5c and 5d.
    Type: Application
    Filed: April 30, 2001
    Publication date: September 20, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Kazuo Tomita
  • Patent number: 6284618
    Abstract: It is possible to obtain a semiconductor device in which a contact and a wiring provided on the contact can be electrically connected well even if a shift of superposition is caused. Sidewalls 5a, 5b, 5c and 5d formed of a conductive material are bonded to side faces of wirings 4a and 4b to be provided on contacts 3a and 3b. Consequently, the wirings 4a and 4b and the contacts 3a and 3b can be electrically connected well through the sidewalls 5a, 5b, 5c and 5d.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: September 4, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Patent number: 6127265
    Abstract: After forming the first contact embedded in the first insulating film, a wire is formed on the first contact and a side wall made of an insulative substance is formed on a side surface of the wire. The second insulating film made of a substance different from the side wall is layered in a region including the wire, and a via hole for embedding the second contact is provided in the second insulating film under such an etching condition that the side wall is harder to etch, and therefore an end portion of the wire is not etched and an exposed area of an internal wall of the via hole can be reduced. It is possible to suppress deterioration gap-filling characteristics due to gas discharge from the second insulating film and achieve a contact of good shape. Thus, this structure avoids deterioration in imbedding characteristics that is caused by a deviation of alignment when the wire is interposed between a stacked via consisting of the first and second contacts.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: October 3, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Patent number: 6025645
    Abstract: After forming the first contact embedded in the first insulating film, a wire is formed on the first contact and a side wall made of an insulative substance is formed on a side surface of the wire. The second insulating film made of a substance different from the side wall is layered in a region including the wire, and a via hole for embedding the second contact is provided in the second insulating film under such an etching condition that the side wall is harder to etch, and therefore an end portion of the wire is not etched and an exposed area of an internal wall of the via hole can be reduced. It is possible to suppress deterioration gap-filling characteristics due to gas discharge from the second insulating film and achieve a contact of good shape. Thus, this structure avoids deterioration in imbedding characteristics that is caused by a deviation of alignment when the wire is interposed between a stacked via consisting of the first and second contacts.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: February 15, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Patent number: 6023083
    Abstract: A semiconductor device has a conductive contact buried in a contact hole formed in an insulation film. A conductor pattern is formed on the insulation film and a separate conductive sidewall is formed on a side face of the conductor pattern over or next to the contact buried in the contact hole. The separate conductive sidewall extends on the side face above a top face of the insulation film in a direction away from the top face of the insulation film. This permits the conductor pattern to either be directly in contact with the conductive contact in the contact hole and/or to make good electrical contact with the contact in the contact hole via the separate conductive sidewall.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: February 8, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Patent number: 6023101
    Abstract: A coverage can be improved when an upper layer is formed on an upper wiring patterned on an interlayer insulation film. A sidewall made of an insulating material is bonded to a side face of the upper wiring patterned on the interlayer insulation film. Consequently, a height difference between the upper wiring and the interlayer insulation film has a small gradient. By flattening a laminated face of the upper layers including surfaces of the upper wiring and the sidewall, a further upper layer to be formed can have a coverage improved.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: February 8, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuo Tomita
  • Patent number: 5963384
    Abstract: A signal recording device is provided for transmitting recording data signals via a rotary transformer to a rotary drum having a rotary head for recording data so that control data may be transmitted in a shorter time period and resolution along the time axis may be improved. A 1-bit start bit SB and 2-bit mode setting bits PD are followed by 3-bit group bits GP and 3-bit channel bits CL for a single bit mode, by 3-bit group bits GP and an 8-bit bit patterns BP for a multi-bit mode and by a 4-bit channel number DAN and 8-bit data DAD for D/A data. An even parity PE is appended for each of the respective modes. A continuation flag CF is further appended for the single-bit mode and the multi-bit mode.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: October 5, 1999
    Assignee: Sony Corporation
    Inventors: Minoru Kawahara, Hitoshi Tsujii, Kazuo Tomita
  • Patent number: 4892882
    Abstract: Compounds of formula (I): ##STR1## (wherein: R.sup.1 represents a hydrogen atom or a halogen atom;R.sup.2 represents a C.sub.1 -C.sub.6 alkyl group; andA represents an oxygen atom, a sulphur atom, a sulphinyl group or a sulphonyl group)have good insecticidal activity coupled with a low toxicity to warm-blooded animals. Compounds in which A represents an oxygen or sulphur atom can be prepared by reacting a corresponding alkali metal alkoxide or mercaptide with the corresponding 3-dimethylcarbamoyloxy-5-halomethylisoxazole derivative, while compounds where A represents a sulphinyl or sulphonyl group may be prepared by oxidizing the corresponding compound wherein A represents a sulphur atom. The compounds may be formulated with conventional insecticidal carriers or diluents and exhibit a synergistic increase in activity when combined with various known organic phosphate and carbamate insecticides.
    Type: Grant
    Filed: January 18, 1985
    Date of Patent: January 9, 1990
    Assignee: Sankyo Company Limited
    Inventors: Kazuo Tomita, Tadashi Murakami, Hideakira Tsuji, Keigo Matsumoto, Katsuhiro Fujita
  • Patent number: 4714965
    Abstract: In a time base corrector for correcting time base fluctuations of signals reproduced from a record medium, on which a plurality of time-compressed component signals occurring within one horizontal period in a predetermined sequential order are recorded in response to a clock signal with a predetermined frequency, a write clock pulse generator used in the time base corrector includes a phase shifter for shifting the phase of an incoming write clock signal, whereby the write clock signal having a frequency different from the predetermined frequency is generated in response to a horizontal synchronizing signal, the start time of each of the plurality of reproduced component signals is detected and the shifting amount of the write clock signal by the phase shifter is switched in accordance with the detected output so as to synchronize the write clock signal with the start time of each of the reproduced component signal.
    Type: Grant
    Filed: December 11, 1985
    Date of Patent: December 22, 1987
    Assignee: Sony Corporation
    Inventors: Tadaaki Yoshinaka, Takao Inoue, Kazuo Tomita
  • Patent number: 4634774
    Abstract: 3-hydroxy-5-methylisoxazole is prepared by reacting diketene in a continuous process with hydroxylamine to give a reaction mixture containing acetoacetohydroxamic acid and then acidifying this reaction mixture as quickly as possible to produce the 3-hydroxy-5-methylisoxazole.
    Type: Grant
    Filed: April 5, 1984
    Date of Patent: January 6, 1987
    Assignee: Sankyo Company Limited
    Inventors: Tadashi Murakami, Kazuo Tomita
  • Patent number: 4622637
    Abstract: An optimum shift timing indicating device for a vehicle includes: a speed sensor for detecting a rotational speed of an engine or a running speed of the vehicle; a load sensor for detecting an engine load; a data processing device having a data map or maps fewer in number than gear positions of the vehicle transmission, said data map or maps having a set shift-up region and/or shift-down region selected in accordance with the rotational speed of the engine or the running speed of the vehicle and the engine load, for emitting a shift-up instruction signal and/or a shift-down instruction signal in accordance with the rotational speed of the engine or the running speed of the vehicle and the engine load; and a shift instructing device for giving a driver a shift-up instruction and/or a shift-down instruction in response to an output from said data processing device; so that instruction about the optimum shift timing can be given to the driver with the use of only a small memory capacity.
    Type: Grant
    Filed: September 22, 1983
    Date of Patent: November 11, 1986
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuo Tomita, Kouhei Igarashi
  • Patent number: 4604700
    Abstract: An apparatus for indicating an optimum time to shift a manual transmission in a vehicle. An electronic control unit is provided to compare the actual gear shift position with the electronically memorized optimum gear shift position. The optimum gear shift position is predetermined by examining the parameters of engine speed, vehicle speed, engine load and engine temperature. If the actual gear shift position differs from the memorized and stored optimum gear shift position, the operator is notified by a shift indicator lamp or loudspeaker.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: August 5, 1986
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kohei Igarashi, Kazuo Tomita
  • Patent number: 4579860
    Abstract: Compounds of formula (I): ##STR1## (wherein R.sup.1 represents a hydrogen or halogen atom R.sup.2 represents an alkyl, alkenyl, alkynyl, optionally substituted aralkyl or optionally substituted aryl group and A represents a sulphur atom or a sulphinyl or sulphonyl group) have insecticidal and acaricidal activity and, when formulated in suitable compositions for agricultural or horticultural use, can be used to protect plants from attack by insects or acarids.
    Type: Grant
    Filed: May 5, 1983
    Date of Patent: April 1, 1986
    Assignee: Sankyo Company, Limited
    Inventors: Kazuo Tomita, Tadashi Murakami, Hideakira Tsuji, Keigo Matsumoto, Katsuhiro Fujita
  • Patent number: 4492112
    Abstract: The optimum shift position indicating device of a vehicle comprising: a vehicle speed sensor for detecting a running speed of the vehicle; an engine rotation sensor for detecting a rotational speed of an engine; an engine load sensor for detecting an engine load; an operational circuit in which a driving power at present is calculated from an engine torque obtainable from the engine rotational speed and the engine load, subsequently, required engine torques at respective shift positions are calculated from the driving power, further, fuel consumption rates at the respective shift positions are obtained from the engine rotational speeds and the required engine torques at the respective shift positions, and information on the optimum shift position where the best fuel consumption rate is obtainable is outputted; and shift position indicating elements for indicating an output from said operational circuit; and capable of giving a driver the information on the optimum shift position where the best fuel consumptio
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: January 8, 1985
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kouhei Igarashi, Kazuo Tomita