Patents by Inventor Kazuo Watanabe

Kazuo Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210282198
    Abstract: In a communication apparatus on a network where communication apparatuses perform direct communication with each other, a network management apparatus for managing the network based on message information transmitted and received on the network is determined. When the communication apparatus itself is determined as the network management apparatus, the apparatus collects information indicating device capabilities from other communication apparatuses. On the other hand, the communication apparatus receives information indicating device capabilities from another communication apparatus when the other communication apparatus is determined as the network management apparatus.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Tatsuhiko Sakai, Kenichi Fujii, Mitsuhiro Watanabe, Kazuo Moritomo
  • Patent number: 11114982
    Abstract: A power amplifier circuit includes an amplifier transistor having a first terminal supplied with a power supply voltage that changes in accordance with an amplitude level of an input signal, and a second terminal supplied with the input signal and a bias current, an amplified signal obtained by amplifying the input signal being outputted from the first terminal, a bias circuit that outputs the bias current from an output terminal thereof in accordance with a reference current supplied to an input terminal thereof, and a regulation circuit that generates a regulation current for regulating the bias current in accordance with a change in the power supply voltage. The regulation current increases with an increase in the power supply voltage, and decreases with a decrease in the power supply voltage. The regulation circuit extracts the regulation current from at least one of the reference current or the bias current.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 7, 2021
    Assignee: MURATA MANUFACTURING CO. , LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Satoshi Arayashiki
  • Publication number: 20210234519
    Abstract: A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 29, 2021
    Inventors: Satoshi TANAKA, Kazuo WATANABE, Yusuke TANAKA, Satoshi ARAYASHIKI
  • Publication number: 20210226595
    Abstract: A power amplifier circuit includes a power amplifier including a first transistor having a first terminal connected to a reference potential, a second terminal to which a first current and a radio-frequency signal are input, and a third terminal connected to a first power supply potential via a first inductor; a capacitor connected to the third terminal of the first transistor; a second transistor including a first terminal connected to the capacitor and the reference potential via a second inductor, a second terminal to which a second current is input and is connected to the reference potential, and a third terminal connected to the first power supply potential via a third inductor and outputs signal; and an adjustment circuit that outputs a third current corresponding to the first power supply potential or a second power supply potential to the second terminal of the second transistor.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Inventors: Jun ENOMOTO, Kazuo WATANABE, Satoshi TANAKA, Yusuke TANAKA, Makoto ITO
  • Publication number: 20210227595
    Abstract: A communication system capable of improving signal processing efficiency even when a plurality of connections are established is provided. A communication system according to the present invention includes a user plane PGW (14) configured to connect to a PDN, a user plane SGW (12) configured to relay user plane data between the user plane PGW (14) and a base station (34), and a control plane SGW (30). Further, the communication system includes a control apparatus (32) configured to, when a plurality of connections are established for the communication terminal (36), transmit information indicating that the user plane PGW (14) and the user plane SGW (12) can be integrally configured to the control plane SGW (30) for each of the plurality of connections.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: NEC Corporatiion
    Inventors: Satoshi Kuroda, Toshiyuki Tamura, Kazuo Watanabe
  • Publication number: 20210194433
    Abstract: A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.
    Type: Application
    Filed: March 9, 2021
    Publication date: June 24, 2021
    Inventors: Satoshi TANAKA, Satoshi ARAYASHIKI, Kazuo WATANABE
  • Publication number: 20210175857
    Abstract: A power amplifier circuit includes first and second bias circuits configured to provide first and second biases, respectively, a first transistor having an emitter connected to a reference potential, a base configured to receive the first bias via a first resistor and receive a radio-frequency input signal via a first capacitor, and a collector configured to output an amplified radio-frequency signal, a second transistor having a base connected to the reference potential via a second capacitor and configured to receive the second bias via a second resistor, an emitter configured to receive the radio-frequency signal, and a collector connected to a power supply potential via a third inductor and configured to output a radio-frequency output signal, and an impedance circuit having a first end connected to an output section of the second bias circuit and configured to apply an alternating-current signal to a path extending from the second bias circuit.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 10, 2021
    Inventors: Jun ENOMOTO, Kazuo WATANABE, Satoshi TANAKA, Yusuke TANAKA, Makoto ITOU
  • Patent number: 10999878
    Abstract: A communication system capable of improving signal processing efficiency even when a plurality of connections are established is provided. A communication system according to the present invention includes a user plane PGW (14) configured to connect to a PDN, a user plane SGW (12) configured to relay user plane data between the user plane PGW (14) and a base station (34), and a control plane SGW (30). Further, the communication system includes a control apparatus (32) configured to, when a plurality of connections are established for the communication terminal (36), transmit information indicating that the user plane PGW (14) and the user plane SGW (12) can be integrally configured to the control plane SGW (30) for each of the plurality of connections.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 4, 2021
    Assignee: NEC CORPORATION
    Inventors: Satoshi Kuroda, Toshiyuki Tamura, Kazuo Watanabe
  • Patent number: 10985715
    Abstract: A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 20, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Yusuke Tanaka, Satoshi Arayashiki
  • Patent number: 10972051
    Abstract: A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: April 6, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Kazuo Watanabe
  • Patent number: 10965325
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 30, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Tetsuaki Adachi, Masahito Numanami, Yasuhisa Yamamoto
  • Patent number: 10944438
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 9, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Tetsuaki Adachi, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20210044262
    Abstract: A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Satoshi ARAYASHIKI, Kazuo WATANABE, Satoshi TANAKA
  • Publication number: 20210006205
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Inventors: Satoshi TANAKA, Tetsuaki ADACHI, Kazuo WATANABE, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Patent number: 10848111
    Abstract: A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: November 24, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Arayashiki, Kazuo Watanabe, Satoshi Tanaka
  • Patent number: 10819286
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 27, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Tetsuaki Adachi, Kazuo Watanabe, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20200321927
    Abstract: A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 8, 2020
    Inventors: Toshikazu TERASHIMA, Fumio HARIMA, Makoto ITOU, Satoshi TANAKA, Kazuo WATANABE, Satoshi ARAYASHIKI, Chikara YOSHIDA
  • Publication number: 20200313629
    Abstract: A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.
    Type: Application
    Filed: March 24, 2020
    Publication date: October 1, 2020
    Inventors: Toshikazu TERASHIMA, Satoshi TANAKA, Kazuo WATANABE, Makoto ITOU, Jun ENOMOTO
  • Publication number: 20200304073
    Abstract: A power amplifier circuit includes an amplifier transistor having a first terminal supplied with a power supply voltage that changes in accordance with an amplitude level of an input signal, and a second terminal supplied with the input signal and a bias current, an amplified signal obtained by amplifying the input signal being outputted from the first terminal, a bias circuit that outputs the bias current from an output terminal thereof in accordance with a reference current supplied to an input terminal thereof, and a regulation circuit that generates a regulation current for regulating the bias current in accordance with a change in the power supply voltage. The regulation current increases with an increase in the power supply voltage, and decreases with a decrease in the power supply voltage. The regulation circuit extracts the regulation current from at least one of the reference current or the bias current.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 24, 2020
    Inventors: Satoshi TANAKA, Kazuo WATANABE, Satoshi ARAYASHIKI
  • Publication number: 20200304071
    Abstract: A power amplifier circuit includes an amplifier that receives an input signal with an alternating current and outputs an output signal obtained by amplifying power of the input signal to a first node; an inductive element that is connected between the first node and a second node; and a variable capacitor that is connected between the second node and a reference potential, and whose electrostatic capacitance increases as power of the output signal increases.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Inventors: Satoshi Tanaka, Masatoshi HASE, Norio HAYASHI, Kazuo WATANABE, Yuuri HONDA