Patents by Inventor Kazuo Watanabe

Kazuo Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11964950
    Abstract: The present disclosure provides, for example, a compound represented by the general formula below or a pharmaceutically acceptable salt thereof, or a pharmaceutically acceptable solvate of the compound or salt: wherein X1, X2, X3 and X4 are each independently —CR2? or N?, R2 is, for example, a halogen atom, R1 is, for example, —S(?O)2—NH—R8, R8 is, for example, a C1-6 alkyl group, R3 is, for example, a hydrogen atom, R5 is, for example, a halogen atom, R6 is, for example, a hydrogen atom, and R4 is, for example, a cyclopropyl group. The compounds, salts or solvates provided by the present disclosure exhibit high RAF/MEK complex-stabilizing activity and can be used for the treatment or prevention of cell proliferative disorders, particularly cancers.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 23, 2024
    Assignee: Chugai Seiyaku Kabushiki Kaisha
    Inventors: Yoshiaki Isshiki, Fumio Watanabe, Masaki Tomizawa, Kihito Hada, Kazuo Hattori, Kenichi Kawasaki, Ikumi Hyodo, Toshihiro Aoki
  • Publication number: 20240117126
    Abstract: A high filler-loaded thermally conductive thin sheet is obtained by uniformly dispersing a mixture containing organic polymer particles and highly thermally conductive filler particles using a pulverizer or a mixer to obtain a powder composition, conveying the powder composition at a constant thickness between two belts of a double belt press device, and continuously heating and pressurizing the powder composition at a temperature higher than or equal to a deflection temperature under load, melting point, or a glass transition temperature of the organic polymer and at a specific pressure and then cooling and solidifying the powder composition in the double belt press device.
    Type: Application
    Filed: February 15, 2022
    Publication date: April 11, 2024
    Inventors: Noriaki TAKAGI, Masakuni TAKAGI, Yuusuke NAGATANI, Daisuke WATANABE, Kazuo MATSUYAMA
  • Patent number: 11948952
    Abstract: In a solid-state imaging device, a photoelectric conversion unit, a transfer transistor, and at least a part of electric charge holding unit, among pixel constituent elements, are disposed on a first semiconductor substrate. An amplifying transistor, a signal processing circuit other than a reset transistor, and a plurality of common output lines, to which signals are read out from a plurality of pixels, are disposed on a second semiconductor substrate.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 2, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuo Yamazaki, Tetsuya Itano, Nobuyuki Endo, Kyouhei Watanabe
  • Patent number: 11942501
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 26, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Publication number: 20240092981
    Abstract: A problem of heat dissipation in motors, converters, high-luminance LEDs, power devices, power supplies, and the like becomes significant. Provided is a means for capable of providing a product, which has favorable workability, segregation stability, storage stability, and the like, penetrates into a gap in a coil portion, an interface in casing, and the like without any gaps, enhances thermal conductivity/heat dissipation properties of a molded product thus obtained, and is excellent in electrical characteristics, toughness/elastic modulus, thermal resistance, thermal cycle properties, and the like, in the case of using the product for a cast molding resin, a pottingmaterial (sealingmaterial), an adhesive, grease, and the like.
    Type: Application
    Filed: October 20, 2023
    Publication date: March 21, 2024
    Applicant: Takagi Chemicals, Inc.
    Inventors: Noriaki Takagi, Masakuni Takagi, Yuusuke Nagatani, Yuuta Terao, Daisuke Watanabe, Kazuo Matsuyama
  • Publication number: 20240088196
    Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Junji Iwata
  • Patent number: 11784609
    Abstract: A power amplifier circuit includes an amplifier that receives an input signal with an alternating current and outputs an output signal obtained by amplifying power of the input signal to a first node; an inductive element that is connected between the first node and a second node; and a variable capacitor that is connected between the second node and a reference potential, and whose electrostatic capacitance increases as power of the output signal increases.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Masatoshi Hase, Norio Hayashi, Kazuo Watanabe, Yuuri Honda
  • Patent number: 11658622
    Abstract: A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 23, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Yusuke Tanaka, Satoshi Arayashiki
  • Patent number: 11616479
    Abstract: A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 28, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Toshikazu Terashima, Fumio Harima, Makoto Itou, Satoshi Tanaka, Kazuo Watanabe, Satoshi Arayashiki, Chikara Yoshida
  • Patent number: 11606066
    Abstract: A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: March 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Kazuo Watanabe
  • Patent number: 11545944
    Abstract: A power amplifier circuit includes a power amplifier including a first transistor having a first terminal connected to a reference potential, a second terminal to which a first current and a radio-frequency signal are input, and a third terminal connected to a first power supply potential via a first inductor; a capacitor connected to the third terminal of the first transistor; a second transistor including a first terminal connected to the capacitor and the reference potential via a second inductor, a second terminal to which a second current is input and is connected to the reference potential, and a third terminal connected to the first power supply potential via a third inductor and outputs signal; and an adjustment circuit that outputs a third current corresponding to the first power supply potential or a second power supply potential to the second terminal of the second transistor.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 3, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jun Enomoto, Kazuo Watanabe, Satoshi Tanaka, Yusuke Tanaka, Makoto Ito
  • Patent number: 11515840
    Abstract: The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: November 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Watanabe, Satoshi Tanaka, Norio Hayashi, Kazuma Sugiura
  • Patent number: 11469715
    Abstract: A power amplifier circuit includes first and second bias circuits configured to provide first and second biases, respectively, a first transistor having an emitter connected to a reference potential, a base configured to receive the first bias via a first resistor and receive a radio-frequency input signal via a first capacitor, and a collector configured to output an amplified radio-frequency signal, a second transistor having a base connected to the reference potential via a second capacitor and configured to receive the second bias via a second resistor, an emitter configured to receive the radio-frequency signal, and a collector connected to a power supply potential via a third inductor and configured to output a radio-frequency output signal, and an impedance circuit having a first end connected to an output section of the second bias circuit and configured to apply an alternating-current signal to a path extending from the second bias circuit.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: October 11, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jun Enomoto, Kazuo Watanabe, Satoshi Tanaka, Yusuke Tanaka, Makoto Itou
  • Patent number: 11454836
    Abstract: A laser processing apparatus disclosed in the present application includes: an optical deflection unit capable of changing a deflection direction of and outgoing energy of an incoming laser pulse by changes of a frequency of and an amplitude of a driving signal to be supplied; and a control unit configured to supply driving signals with amplitudes corresponding to respective frequencies. In a laser processing apparatus configured to process a workpiece by leading outgoing laser pulse of the optical deflection unit to the workpiece and irradiating the workpiece with the laser pulse, as the amplitude corresponding to each of the frequencies, the control unit supplies an amplitude having the ratio that is close to the lowest ratio among ratios of the outgoing energy with respect to the incoming energy of the laser pulse at an amplitude having the largest outgoing energy of the optical deflection unit.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 27, 2022
    Assignee: VIA MECHANICS, LTD.
    Inventors: Kazuya Matsumoto, Kazuo Watanabe, Atsushi Sakamoto, Masanori Sato, Mitsuru Kato, Masaru Kikuchi
  • Publication number: 20220281746
    Abstract: An embodiment of the present invention provides a noble gas hydride having the following formula 1: NgnHm. In formula 1, Ng represents a noble gas atom, n represents an integer from 1-8, and m represents an integer from 1-46.
    Type: Application
    Filed: July 6, 2020
    Publication date: September 8, 2022
    Applicant: TOKYO UNIVERSITY OF SCIENCE FOUNDATION
    Inventor: Kazuo WATANABE
  • Patent number: 11387796
    Abstract: A power amplifier circuit includes a lower-stage transistor having a first power supply voltage supplied to a first terminal, a second terminal connected to ground, and a first signal supplied to a third terminal; an upper-stage transistor having a second power supply voltage supplied to a first terminal, a second signal obtained by amplifying the first signal being output from the first terminal, a second terminal connected to the first terminal of the lower-stage transistor via a first capacitor, and a third terminal connected to ground via a ground path; an inductor that connects the second terminal of the upper-stage transistor to ground; and an adjustment circuit that adjusts impedance seen from the third terminal of the upper-stage transistor. The adjustment circuit includes a second capacitor and at least one resistance element connected in series with the ground path between the third terminal of the upper-stage transistor and ground.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 12, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Norio Hayashi, Makoto Itou
  • Patent number: 11323081
    Abstract: A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Arayashiki, Kazuo Watanabe, Satoshi Tanaka
  • Patent number: 11264952
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Tetsuaki Adachi, Kazuo Watanabe, Masahito Numanami, Yasuhisa Yamamoto
  • Patent number: 11258406
    Abstract: A power amplifier circuit includes a first transistor, a second transistor, a first bias circuit supplying a first bias current or voltage, a second bias circuit supplying a second bias current or voltage, a first inductor, and a first capacitor. A power supply voltage is supplied to a collector of the first transistor, and an emitter thereof is grounded. A radio frequency signal and the first bias current or voltage are supplied to a base of the first transistor. The power supply voltage is supplied to a collector of the second transistor, and an emitter thereof is connected to the collector of the first transistor via the first capacitor and is grounded via the first inductor. The second bias current or voltage is supplied to a base of the second transistor. An amplified radio frequency signal is output from the collector of the second transistor.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Masatoshi Hase, Yuri Honda, Kazuo Watanabe, Takashi Soga
  • Patent number: 11245365
    Abstract: A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: February 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Toshikazu Terashima, Satoshi Tanaka, Kazuo Watanabe, Makoto Itou, Jun Enomoto