Patents by Inventor Kazuo Yamakido
Kazuo Yamakido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110115569Abstract: The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.Type: ApplicationFiled: January 20, 2011Publication date: May 19, 2011Inventors: KAZUO YAMAKIDO, Takashi Nakamura
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Patent number: 7888981Abstract: The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.Type: GrantFiled: August 6, 2010Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Kazuo Yamakido, Takashi Nakamura
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Publication number: 20100295585Abstract: The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.Type: ApplicationFiled: August 6, 2010Publication date: November 25, 2010Inventors: KAZUO YAMAKIDO, Takashi Nakamura
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Patent number: 7786776Abstract: The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.Type: GrantFiled: February 4, 2009Date of Patent: August 31, 2010Assignee: Renesas Technology Corp.Inventors: Kazuo Yamakido, Takashi Nakamura
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Publication number: 20090195277Abstract: The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.Type: ApplicationFiled: February 4, 2009Publication date: August 6, 2009Inventors: Kazuo YAMAKIDO, Takashi Nakamura
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Patent number: 6963298Abstract: An AD converter which uses no buffer for receiving the input signals or uses the buffer having relaxed requirements concerning the range of input signals and the output impedance. Voltage at the connection points of a resistor ladder in which a plurality of resistor elements are connected in series, are compared with a reference voltage by a plurality of voltage comparators, a first current circuit is provided on the high potential side of the resistor ladder, a second current circuit is provided on the low potential side thereof, and analog input voltages are fed by providing an input terminal at any place of the resistor ladder except both ends thereof.Type: GrantFiled: May 23, 2002Date of Patent: November 8, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masanori Otsuka, Kazuo Yamakido, Etsuji Yamamoto, Shinya Sano
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Publication number: 20030043066Abstract: An AD converter which uses no buffer for receiving the input signals or uses the buffer having relaxed requirements concerning the range of input signals and the output impedance. Voltages at the connection points of a resistor ladder in which a plurality of resistor elements are connected in series, are compared with a reference voltage by a plurality of voltage comparators, a first current circuit is provided on the high potential side of the resistor ladder, a second current circuit is provided on the low potential side thereof, and analog input voltages are fed by providing an input terminal at any place of the resistor ladder except both ends thereof.Type: ApplicationFiled: May 23, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Masanori Otsuka, Kazuo Yamakido, Etsuji Yamamoto, Shinya Sano
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Patent number: 5515047Abstract: The number of current sources and switches necessary for a plurality of unit D/A converters using equal reference currents, are drastically reduced to reduce the parasitic capacitance coupled to current output lines, by converting a plurality of digital signals of a predetermined bit, which are divided from an input digital signal, into an analog current unit D/A converters and by converting the analog current in a manner to correspond to the weights of the corresponding input digital signals, thereby to synthesize the currents. The fixed reference digital signal is inputted to the D/A converter for cancelling offsets. The offsets of a plurality of analog output signals in positive and opposite phases obtained by branching the output of the D/A converter are individually detected. After this, the DC offset values of the individual analog outputs are used as offset adjusted negative feedback signals for a desired value.Type: GrantFiled: December 20, 1993Date of Patent: May 7, 1996Assignee: Hitachi, Ltd.Inventors: Kazuo Yamakido, Yoichiro Kobayashi, Masanori Otsuka, Takao Okazaki, Yukihito Ishihara, Norimitsu Nishikawa, Yuko Tamba
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Patent number: 5406218Abstract: A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.Type: GrantFiled: February 9, 1994Date of Patent: April 11, 1995Assignee: Hitachi, Ltd.Inventors: Yukihito Ishihara, Kazuo Yamakido, Takao Okazaki, Katsuhiro Furukawa
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Patent number: 5392456Abstract: A method of controlling the time constant of a filter for use in a radio receiver which receives a signal, transmitted from a transmitting station at a predetermined period, intermittently at the predetermined period and demodulates and delivers the received signal, a filter circuit having the time constant control function based on the method, and a radio receiver having the filter circuit. Preferably, the filter has its time constant switchable stepwise and specifically, parallel connection of capacitors or shortcircuiting of resistors is controlled by turning on/off switches.Type: GrantFiled: October 3, 1990Date of Patent: February 21, 1995Assignees: Hitachi, Ltd., Kokusai Electric Co., Ltd.Inventors: Isamu Mitomo, Nobuo Tsukamoto, Arata Nakagoshi, Jiroh Sakaguchi, Kazuo Yamakido, Hiroshi Noguchi, Atushi Hoshi
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Analog/digital converter of the over-sampling type with feedback correction to offset sampling error
Patent number: 5347279Abstract: The difference between the output current of a voltage-current converter circuit and the output current of a local D/A converter circuit 2, whose output current is controlled by a feedback signal, is integrated by an analog circuit of which one end is connected to a DC potential point, and the voltage obtained by the integration thereof is quantized by a quantizing circuit. The result is integrated by a digital integrating circuit and is fed to a feedback correcting circuit 6 and, further, the result of A/D conversion is output. The feedback correcting circuit outputs a temporary feedback signal while the digital integration is being operated based on the output of the quantizing circuit. After the digital integrating operation completes the digital integration operation, a corrected feedback signal is generated instead of the temporary feedback signal. The signals inputted into the analog circuit 3 are continuously sampled even while the digital integration operation is being carried out.Type: GrantFiled: September 2, 1992Date of Patent: September 13, 1994Assignee: Hitachi, Ltd.Inventors: Yukihito Ishihara, Kazuo Yamakido, Yuko Tamba -
Patent number: 5227795Abstract: An over-sampling analog-to-digital converter using a current switching circuit 102 as a local digital-to-analog converter, wherein a difference between the output currents Isig and Iq of a voltage-to-current converter circuit 101 and a current switching circuit is integrated by a capacitor 105 of which the one end is grounded to a dc potential VB. Further, the current switching circuit 102 has many bits to decrease the difference current between the signal current Isig and the feedback current signal Iq. Moreover, the level-shifting function of the voltage-to-current converter circuit 101 makes it possible to apparently subtract the dc component from the input analog signal Vsig which is produced based on an internally generated dc voltage as a dc bias voltage, and to decrease a change in the voltage between the electrodes of a capacitor caused by the integration of current.Type: GrantFiled: May 23, 1991Date of Patent: July 13, 1993Assignee: Hitachi, Ltd.Inventors: Kazuo Yamakido, Norimitsu Nishikawa, Katsuhiro Furukawa, Yuko Tamba, Takao Okazaki
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Patent number: 5157398Abstract: In an A/D convertor, one comparator is provided for the most significant bit of the output digital signal, two for the second bit, and three each for the third and lower-order bits. When a compare operation is being performed by one of the three comparators that are provided for each of the third and lower bits, the remaining two comparators provide outputs in response to which output switch circuits perform setting of two reference voltages that are specified by the comparison result of a comparator corresponding to an output digital signal two bits higher.Type: GrantFiled: October 17, 1991Date of Patent: October 20, 1992Assignee: Hitachi, Ltd.Inventors: Takao Okazaki, Kazuo Yamakido
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Patent number: 4945359Abstract: Herein disclosed is an oversampling type A/D converter, wherein there are connected in multiple stages units interpolation type A/D conversion circuits each including: an analog integration circuit for integrating the difference between an analog input signal and a feedback signal; a voltage comparison circuit for adding the integrated signal and said difference to produce a digital signal on the basis of the added value; a digital integration circuit for integrating the digital signal coming from the voltage comparison circuit; a feedback load D/A conversion circuit for producing a feedback signal from the output of the digital integration circuit; and an addition circuit for adding the output and input of said digital integration circuit.Type: GrantFiled: March 21, 1989Date of Patent: July 31, 1990Assignee: Hitachi, Ltd.Inventor: Kazuo Yamakido
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Patent number: 4796296Abstract: A CODEC including a coder and decoder to construct the subscriber's circuit of a digital telephone switching system or the like, wherein an analogue balancing circuit is provided between the output terminal of a post-filter and the input terminal of a pre-filter in order to effectively eliminate a return signal in the case of two-wire/four-wire conversion, and return signals not eliminated by the analogue balancing circuit are further eliminated by a digital balancing circuit.Especially in the present invention, the analogue balancing circuit is so constructed that its characteristics are independent of frequencies, and hence, the analogue balancing circuit and the digital balancing circuit are readily implemented as an LSI.Type: GrantFiled: May 30, 1985Date of Patent: January 3, 1989Assignee: Hitachi, Ltd.Inventors: Eiichi Amada, Kazuo Yamakido, Takahiko Kozaki, Shigeo Nishita, Masaru Kokubo
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Patent number: 4787080Abstract: A PCM coder and decoder circuit for use in a subscriber line interface circuit of a telephone communication system has a digital balancing network for removing any echo signal. The digital balancing network is formed by series-connecting a first balancing circuit having characteristics corresponding to the fixed characteristics of a coder, decoder, etc. and a second balancing circuit having characteristics corresponding to variable characteristics of an external circuit including two-wire transmission line which is connected to the coder and decoder circuit. Thus, a replica of an echo signal is precisely produced, and the circuit configuration is simplified.Type: GrantFiled: August 8, 1986Date of Patent: November 22, 1988Assignees: Hitachi Ltd., Hitachi Micro Computer Eng. Ltd.Inventors: Kazuo Yamakido, Takahiko Kozaki, Shigeo Nishita, Kenichi Ohwada
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Patent number: 4672361Abstract: Disclosed is an interpolative A/D converter for converting an over-sampled analog signal into a digital signal without the occurrence of over slope distortions, wherein the difference between the analog input signal and an analog feedback signal derived from the converter output through D/A conversion is integrated, the integrated output is compared with several reference voltages and, after being converted into a digital signal, the comparison result is integrated in a digital manner to complete a digital output signal of the A/D converter.Type: GrantFiled: August 26, 1985Date of Patent: June 9, 1987Assignee: Hitachi, Ltd.Inventors: Masaru Kokubo, Shigeo Nishida, Kazuo Yamakido
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Patent number: 4652858Abstract: An oversampling type digital-to-analog converter which has a light gradient overload and a high signal-to-noise ratio in spite of a comparatively low sampling frequency.In a digital-to-analog converter wherein the difference between an oversampled digital input signal and a feedback signal is taken, such differences are integrated, the integral value is quantized to obtain the feedback signal, and part of the feedback signal is used as an analog output signal; a circuit for the quantization is constructed of a circuit which converts the integral value into a digital signal smaller in the number of bits than the digital input signal, and the feedback signal is obtained by integrating the outputs of the quantization circuit by means of a digital integral circuit.Type: GrantFiled: April 16, 1986Date of Patent: March 24, 1987Assignee: Hitachi, Ltd.Inventors: Masaru Kokubo, Shigeo Nishita, Kazuo Yamakido
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Patent number: 4603417Abstract: In order to realize a system in which three or more subscriber parties can hold a conference, and a PCM decoder is also provided with a circuit which adds part of a received digital PCM signal on the input side of the PCM decoder to a PCM signal corresponding to the output of the PCM coder.Type: GrantFiled: October 9, 1984Date of Patent: July 29, 1986Assignee: Hitachi, Ltd.Inventors: Hirotoshi Shirasu, Kazuo Yamakido
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Patent number: RE32313Abstract: A PCM encoder for converting a voice signal into a eight-bit code by approximating the .mu.-low characteristic where .mu.=255 with 15 segments comprises a capacitor array circuit including eight capacitors for determining lowermost voltages of the segments, a resistor string circuit for producing step voltage in each of the segments, a comparator circuit for comparing the output voltage of the capacitor array circuit with a reference voltage, and a successive approximation register circuit for controlling switch groups provided in the capacitor array circuit and the resistor string circuit. The resistor string circuit is provided with taps for deriving voltages corresponding to (2n-1)/33 (where n=1-16) of a voltage applied across the resistor string. A PCM encoder which conforms to the .mu.-low with high fidelity and is capable of quantizing mid-tread at the first segment is disclosed.Type: GrantFiled: January 17, 1985Date of Patent: December 23, 1986Assignee: Hitachi, Ltd.Inventor: Kazuo Yamakido