Abstract: In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area).

Abstract: A semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against the noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size.

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract: The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc.

Abstract: A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.

Abstract: The present invention intends to prevent generation of metallic noise when both longitudinal sides of the chain supporting trolley (22) installed to the center link (19) of the chain collide against the ends of the adjoining side links (20a, 20b, 25) when the driving chains (18) which comprise linkchains in which a center link (19) whose plane shape is an elongated ring and a pair of top and bottom side links (20a, 20b, 25) are linked alternately become loose.

Abstract: An electorphotographic photoreceptor comprises an electroconductive support at least whose indentation hardness of surface is 100 and over on the Vickers hardness scale; a photoconductive layer comprising amorphous silicon containing at least one of hydrogen and halogen; and a surface layer comprising at least one of an amorphous silicon layer containing at least one of nitrogen, oxygen, and carbon, and an amorphous carbon layer containing at least one of not exceeding 50 atm. % of hydrogen and halogen. This photoreceptor is long-lived and causing no image defects that would otherwise develop in connection with the support, and it can be applied to an energy-saving, low-cost and highly reliable electrophotographic process and apparatus.

Abstract: A flexible pipe joint capable of joining connecting portions of connected objects such as pipes to each other while permitting the direction of joining between both to be varied as desired. First and second joint members (11,31) are formed with spherical inner surfaces (13,37) which slidably contact spherical outer surfaces (54,56) on an interpolating member (51) located between the joint members. Thus, the interpolating member (51) is rockable relative to the joint members (11,31) about the centre of each of the spherical outer surfaces (54,56). Press rings (16,40) are arranged to keep both spherical outer (54,56) and inner (13,37) surfaces in contact with each other through bearing balls (23,47).

Abstract: A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET.

Abstract: An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.

Abstract: In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

Abstract: In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

Abstract: A pipe fitting capable of minimizing flow resistance, decreasing force required for connection and preventing leakage of fluid therethrough. An operating sleeve slidably mounted on a main member of a socket body is forcedly thrusted and a connecting member of a connecting plug is fitted in an internal passage of the main member while pushing away balls fitted in the main member, so that the connecting member forcedly pushes an on-off valve arranged in the main member to pivotally move it for opening it. Releasing of the operating sleeve from its thrusted position causes the balls to be fitted in an annular groove of the connecting plug, to thereby accomplish connection between the socket body and the connecting plug.

Abstract: A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.

Abstract: An AFC/AGC circuit utilized in a receiving apparatus of a ground station for the satellite communication system comprising a digital AFC/AGC controller functioning such that;when the pilot signal is not received, the gain control voltage and the frequency control voltage are respectively set to appropriate values based on the predetermined data;when the pilot signal starts to be received, the gain and frequency control voltages are switched from the set values to the values obtained from the digital AFC and AGC processings, respectively;so long as the pilot signal is being received, the signal generated in the digital AFC and AGC processings are sampled by respective sampling clock signals and the gain and frequency control voltages are determined in accordance with the sampled data; andwhen the pilot signal stops being received, each of the gain and frequency control voltages is held at the value sampled by a last pulse of the sampling clock signal immediately before the stopping, respectively.

Abstract: A hose fitting which comprises a body having a longitudinal fluid passage adapted to receive a hose, an O-ring provided in the fluid passage so as to give water- or air-tightness to a space formed between the outside surface of the hose inserted in the fluid passage and the surrounding wall thereof, a quick hose-disconnecting mechanism provided between the O-ring and the outlet of a fluid passage for gripping the hose in such a manner as to prevent reverse motion and disconnecting the hose by the aid of a single manual pressing operation, and a rotary joint provided rotatably at the inlet end of the fluid passage and adapted to be connected to a fluid supply source.