Patents by Inventor Kazushi Akie
Kazushi Akie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Video encoding device, operating methods thereof, and vehicles equipped with a video encoding device
Patent number: 11606552Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.Type: GrantFiled: July 20, 2021Date of Patent: March 14, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Maiki Hosokawa, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki, Tomohiro Une, Kazushi Akie -
VIDEO ENCODING DEVICE, OPERATING METHODS THEREOF, AND VEHICLES EQUIPPED WITH A VIDEO ENCODING DEVICE
Publication number: 20210352278Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.Type: ApplicationFiled: July 20, 2021Publication date: November 11, 2021Inventors: Maiki HOSOKAWA, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Tomohiro UNE, Kazushi AKIE -
Video encoding device, operating methods thereof, and vehicles equipped with a video encoding device
Patent number: 11102475Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.Type: GrantFiled: October 24, 2019Date of Patent: August 24, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Maiki Hosokawa, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki, Tomohiro Une, Kazushi Akie -
Patent number: 10986373Abstract: An image encoding device includes an encoding circuit configured to encode an image, the image being constituted of a plurality of columns and a plurality of rows of which width are longer than the columns, generate a reference image and stores the reference image into a memory, and output a bit stream including the encoded image. The image encoding device also includes an image rotation circuit configured to rotate the image read from the memory by 90° and output the rotated image to a encoding processing circuit, and a read address generating circuit configured to read the column of the image from the memory, and provide the column with the image rotation circuit.Type: GrantFiled: July 12, 2017Date of Patent: April 20, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Seiji Mochizuki, Kazushi Akie, Tetsuya Shibayama, Kenichi Iwata
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VIDEO ENCODING DEVICE, OPERATING METHODS THEREOF, AND VEHICLES EQUIPPED WITH A VIDEO ENCODING DEVICE
Publication number: 20200195918Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.Type: ApplicationFiled: October 24, 2019Publication date: June 18, 2020Inventors: Maiki HOSOKAWA, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Tomohiro UNE, Kazushi AKIE -
Patent number: 10419753Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.Type: GrantFiled: September 8, 2017Date of Patent: September 17, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazushi Akie, Seiji Mochizuki, Toshiyuki Kaya, Katsushige Matsubara, Hiroshi Ueda, Ren Imaoka, Ryoji Hashimoto
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Patent number: 10356437Abstract: A moving image encoding apparatus executes moving image encoding of a syntax element relating to a moving image signal VS to form an encoded bitstream CVBS. Padding processing of adding padding processing data PD to the moving image signal VS is executed prior to the moving image encoding. Then it is determined whether the encoded block of the syntax element belongs to the moving image signal VS or the padding processing data PD. In the case that the encoded block belongs to the former, an encoded bitstream having a large code amount is formed. In the case where the encoded block belongs to the latter, an encoded bitstream having a small code amount is formed.Type: GrantFiled: July 22, 2013Date of Patent: July 16, 2019Assignee: Renesas Electronics CorporationInventors: Ryoji Hashimoto, Kenichi Iwata, Kazushi Akie
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Publication number: 20180288418Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Inventors: Ren IMAOKA, Seiji MOCHIZUKI, Toshiyuki KAYA, Kazushi AKIE, Ryoji HASHIMOTO
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Patent number: 10021397Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.Type: GrantFiled: September 15, 2016Date of Patent: July 10, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ren Imaoka, Seiji Mochizuki, Toshiyuki Kaya, Kazushi Akie, Ryoji Hashimoto
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Publication number: 20180077413Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.Type: ApplicationFiled: September 8, 2017Publication date: March 15, 2018Inventors: Kazushi AKIE, Seiji MOCHIZUKI, Toshiyuki KAYA, Katsushige MATSUBARA, Hiroshi UEDA, Ren IMAOKA, Ryoji HASHIMOTO
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Publication number: 20170311001Abstract: An image encoding device includes an encoding circuit configured to encode an image, the image being constituted of a plurality of columns and a plurality of rows of which width are longer than the columns, generate a reference image and stores the reference image into a memory, and output a bit stream including the encoded image. The image encoding device also includes an image rotation circuit configured to rotate the image read from the memory by 90° and output the rotated image to a encoding processing circuit, and a read address generating circuit configured to read the column of the image from the memory, and provide the column with the image rotation circuit.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Inventors: Seiji Mochizuki, Kazushi Akie, Tetsuya Shibayama, Kenichi Iwata
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Patent number: 9619228Abstract: The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.Type: GrantFiled: March 28, 2011Date of Patent: April 11, 2017Assignee: Renesas Electronics CorporationInventors: Takafumi Yuasa, Hiroaki Nakata, Motoki Kimura, Kazushi Akie
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Publication number: 20170094280Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.Type: ApplicationFiled: September 15, 2016Publication date: March 30, 2017Inventors: Ren IMAOKA, Seiji MOCHIZUKI, Toshiyuki KAYA, Kazushi AKIE, Ryoji HASHIMOTO
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Publication number: 20160156926Abstract: A moving image encoding apparatus executes moving image encoding of a syntax element relating to a moving image signal VS to form an encoded bitstream CVBS. Padding processing of adding padding processing data PD to the moving image signal VS is executed prior to the moving image encoding, and the horizontal and vertical sizes of an additional moving image signal added the padding processing data are set to an integral multiple of an encoded block size in the moving image encoding. It is determined that the encoded block of the syntax element belongs to which of the moving image signal VS and the padding processing data PD. In a case where the encoded block belongs to the former, an encoded bitstream having a large code amount is formed. In a case where the encoded block belongs to the latter, an encoded bitstream having a small code amount is formed.Type: ApplicationFiled: July 22, 2013Publication date: June 2, 2016Inventors: Ryoji HASHIMOTO, Kenichi IWATA, Kazushi AKIE
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Patent number: 8884792Abstract: Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.Type: GrantFiled: September 4, 2012Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Publication number: 20120326899Abstract: Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Inventors: Hiroaki NAKATA, Fumitake Izuhara, Kazushi Akie, Takafumi Yuasa
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Publication number: 20120294373Abstract: The moving image encoding method includes encoding macro-blocks included in a landscape picture frame of a moving image having a larger horizontal width in a horizontal direction than a vertical width in a vertical direction by an encoding device. In macro-block encoding, information of the encoded macro-blocks surrounding a macro-block to be encoded is stored in a built-in information storing memory of the encoding device. Further, in the encoding, first a vertical array of macro-blocks at the left end of the horizontal width of the landscape picture frame are encoded sequentially, and the resultant encode information is stored in the information storing memory, and subsequently an adjacent vertical array of the plural macro-blocks located horizontally on the right of the left end of the horizontal width of the landscape picture frame are encoded sequentially.Type: ApplicationFiled: December 14, 2010Publication date: November 22, 2012Applicant: Renesas Electronics CorporationInventors: Seiji Mochizuki, Kazushi Akie, Tetsuya Shibayama, Kenichi Iwata
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Patent number: 8264386Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.Type: GrantFiled: December 6, 2010Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Publication number: 20110238964Abstract: The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.Type: ApplicationFiled: March 28, 2011Publication date: September 29, 2011Inventors: Takafumi YUASA, Hiroaki Nakata, Motoki Kimura, Kazushi Akie
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Publication number: 20110080308Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.Type: ApplicationFiled: December 6, 2010Publication date: April 7, 2011Inventors: Hiroaki NAKATA, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa