Abstract: A distributed storage places data units and parity units constituting a stripe formed by divided data into storage nodes in a distributed manner. In reference to determination formulas, either a full-stripe parity calculation method or an RPM parity calculation method is selected so as to minimize an amount of network traffic.

Abstract: A charging assistant system that assists charging for use of an accelerator unit, which is one or more accelerators, includes an operation amount obtaining unit, an acceleration rate estimation unit, and a use fee determination unit. For each of one or more commands input into the accelerator unit, the operation amount obtaining unit obtains the amount of operation related to execution of the command from a response output from the accelerator unit for the command. For the one or more commands input into the accelerator unit, the acceleration rate estimation unit estimates an acceleration rate on the basis of command execution time that is time required for processing of the one or more commands, and one or more amounts of operation obtained for the one or more commands respectively. The use fee determination unit determines a use fee of the accelerator unit on the basis of the estimated acceleration rate.

Abstract: It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.

Abstract: A distributed storage places data units and parity units constituting a stripe formed by divided data into storage nodes in a distributed manner. In reference to determination formulas, either a full-stripe parity calculation method or an RPM parity calculation method is selected so as to minimize an amount of network traffic.

Abstract: The data processing times of data processing nodes are heterogeneous, and hence the execution time of a whole system is not optimized. A task is executed using a plurality of optimal computing devices by distributing a data amount of data to be processed with a processing command of the task for the plurality of optimal computing devices depending on a difference in computing power between the plurality of optimal computing devices, to thereby execute the task in a distributed manner using the plurality of optimal computing devices.

Abstract: An FPGA includes a CRAM that records configuration data for defining a circuit configuration, a main circuit unit of which the circuit configuration is determined according to the configuration data, and an error detection unit that executes memory check processing of detecting whether or not any error is present in the configuration data. A control unit causes the main circuit unit to sequentially execute a plurality of sub-processing steps obtained by segmenting predetermined processing upon receiving a query requesting execution of the predetermined processing to execute the predetermined processing and enables the error detection unit to execute the memory check processing for each of the sub-processing steps.

Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.

Abstract: Processing performance is improved through introduction of accelerators and availability of the system is enhanced during introduction of the accelerators. A worker node includes a processor such as CPU, an accelerator that executes accelerator processing on a command, and a software model that operates on the CPU and executes software model processing of the command. In the worker node, the CPU breaks down an accelerator operator included in a query plan into a plurality of accelerator commands, sends each of the accelerator commands to the accelerator or the software model, and switches the destination of the accelerator command from the accelerator to the software model when a switching condition for changing the processing component of the accelerator command is satisfied.

Abstract: It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.

Abstract: The processor provides a host computer with a logical volume based on a physical storage device. Based on a command from the host computer, the control device writes, into a memory, address information that associates a logical address in the logical volume with a device address in the physical storage device. The control device receives a command from the host computer and if it is determined that the command is a read command, identifies a first logical address designated by the command and determines whether or not the first logical address is included in the address information. If the first address is included in the address information, the control device specifies a first device address corresponding to the first logical address, reads read data stored in an area indicated by the first device address, and transmits the read data to the host computer.

Abstract: The data processing times of data processing nodes are heterogeneous, and hence the execution time of a whole system is not optimized. A task is executed using a plurality of optimal computing devices by distributing a data amount of data to be processed with a processing command of the task for the plurality of optimal computing devices depending on a difference in computing power between the plurality of optimal computing devices, to thereby execute the task in a distributed manner using the plurality of optimal computing devices.

Abstract: An accelerator is mounted on each server which is a worker node of a distributed DB system; a query generated by an application of an application server is divided into a first task that should be executed by the accelerator and a second task that should be executed by software and is allocated to the server of the distributed DB system; the server causes the accelerator to execute the first task, and executes the second task based on the software.

Abstract: An information processing device and a method having high processing performance are proposed. Provided is an information processing device mounted with an accelerator that executes predetermined processing on data, the information processing device including: a storage device configured to store data; and a host control unit configured to request the accelerator to execute the predetermined processing included in a task requested from an outside, in which the data is compressed and stored in the storage device, and in which the accelerator: reads the data to be processed among the data stored in the storage device and executes the predetermined processing on the data while decompressing the read data in response to a request from the host control unit.

Abstract: A charging assistant system that assists charging for use of an accelerator unit, which is one or more accelerators, includes an operation amount obtaining unit, an acceleration rate estimation unit, and a use fee determination unit. For each of one or more commands input into the accelerator unit, the operation amount obtaining unit obtains the amount of operation related to execution of the command from a response output from the accelerator unit for the command. For the one or more commands input into the accelerator unit, the acceleration rate estimation unit estimates an acceleration rate on the basis of command execution time that is time required for processing of the one or more commands, and one or more amounts of operation obtained for the one or more commands respectively. The use fee determination unit determines a use fee of the accelerator unit on the basis of the estimated acceleration rate.

Abstract: The storage system has one or more storage drives, and one or more controllers for receiving processing requests from a superior device, wherein each of the one or more controllers has a processor for executing the processing request and an accelerator, and the accelerator has multiple internal data memories and an internal control memory, wherein if the processing request is a read I/O request, it stores a control information regarding the request to the internal control memory, and reads data being the target of the relevant request from at least one storage drive out of the multiple storage drives, which is temporarily stored in the one or more said internal data memories, and transferred sequentially in order from the internal data memory already storing data to the superior device.

Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.

Abstract: A memory stores: a communication driver that is a software program which runs in an operating system and communicates with a host; and a storage service program that is a software program which runs on the operating system and controls retention of data by a storage apparatus as a storage. The processor is capable of configuring a plurality of queue pairs which transmit information in inter-process communication between the communication driver and the storage service program, and the processor further configures command distribution information which associates a queue pair and a logical volume with each other, specifies a queue pair corresponding to a logical volume that is an access destination of a command requested by the host, and enqueues a command request of the command to the specified queue pair.

Abstract: The processor provides a host computer with a logical volume based on a physical storage device. Based on a command from the host computer, the control device writes, into a memory, address information that associates a logical address in the logical volume with a device address in the physical storage device. The control device receives a command from the host computer and if it is determined that the command is a read command, identifies a first logical address designated by the command and determines whether or not the first logical address is included in the address information. If the first address is included in the address information, the control device specifies a first device address corresponding to the first logical address, reads read data stored in an area indicated by the first device address, and transmits the read data to the host computer.

Abstract: The storage system has one or more storage drives, and one or more controllers for receiving processing requests from a superior device, wherein each of the one or more controllers has a processor for executing the processing request and an accelerator, and the accelerator has multiple internal data memories and an internal control memory, wherein if the processing request is a read I/O request, it stores a control information regarding the request to the internal control memory, and reads data being the target of the relevant request from at least one storage drive out of the multiple storage drives, which is temporarily stored in the one or more said internal data memories, and transferred sequentially in order from the internal data memory already storing data to the superior device.

Abstract: A computer system includes a first storage control module and at least one server module. The first storage control module includes plural storage processors. Each server module includes a server processor and a server I/F connected to the server processor and at least two of the plurality of storage processors. The sever I/F of an issuance server which is any one of the at least one server module specifies the storage processor by referring to sorting information in which identification information of the issuance server of an I/O request issued by the server processor of the issuance server, identification information of a destination storage area of the I/O request, and identification information of the storage processor in charge of the destination storage area are correlated with each other, and sends a command based on the I/O request to the specified storage processor.