Abstract: A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.

Abstract: A data storage apparatus comprising a scrambling circuit 34 for converting address signals and error data output by a tester 24 to a desired format, and a storage device 28 for storing the converted data. The scrambling circuit 34 includes a plurality of conversion circuits 40, 42 and 44 each converting the signals from the tester 24 according to different rules, and a selector 46 for selecting one of signals output by the conversion circuits 40, 42 and 44 and for supplying what is selected to the storage device.

Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A semiconductor module that comprises a plurality of semiconductor chips mounted on a single substrate and which readily diagnoses all the semiconductor chips. A plurality of semiconductor chips are mounted on a single substrate. The semiconductor module is provided with a mode signal pin for receiving a mode signal for requesting performance of a diagnostic operation, as well as with a result output pin for outputting diagnostic results. Further, each of the semiconductor chips is provided with a diagnostic circuit for diagnosing the status of the corresponding semiconductor chip. The semiconductor module is also provided with a diagnosis controller for controlling the diagnostic circuits such that all the semiconductor chips are diagnosed in parallel or serially after a mode signal for requesting a diagnostic operation has been supplied to the mode signal pin.

Abstract: An apparatus and a method for testing a semiconductor that can be subjected to the total test in the state of the final product after sealing in the stage of the wafer test in the test of each of a plurality of semiconductor chips sealed together, and can improve the yield of final products. In the assembly step, another chip sealed together with a chip to be measured is mounted on a probe card, and the tester conducts the test of the chip to be measured through a probe needle connected to the chip to be measured. By transmitting a predetermined command, such as writing and/or reading, from a chip to be measured to another chip, the chip to be measured and the other chip are made to execute operations when these chips are sealed together in a package, and the tester is made to analyze the result of operations and to perform pass or fail judgment.

Abstract: A semiconductor device testing method is disclosed which comprises a first process 39, a second process 41 and a third process 43. In the first process 39, a test function part of a semiconductor device having a built-in self-test function is subjected to a self-diagnostic test, and a main circuit part of the device in question is tested by its test function part. If the result of either of the two tests on the device turns out to be abnormal, the device in question is rejected as defective. The test results are saved. In the second process 41, the main circuit part of each semiconductor device rejected as defective in the first process 39 is tested by use of an external test signal. If the result of the test on the semiconductor device judged faulty in the first process 39 turns out to be normal in the second process 41, then the device in question is judged normal in the third process 43.

Abstract: A replacement information storage unit stores additional replacement information determined according to testing carried out during or after assembly. A replacement information addition load unit receives additional replacement information from outside a plurality of memory chips. A replacement data retain unit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip, and can alter the output address signal according to externally applied additional replacement information.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A replacement information storage unit stores additional replacement information determined according to testing carried out during or after assembly. A replacement information addition load unit receives additional replacement information from outside a plurality of memory chips. A replacement data retain unit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip, and can alter the output address signal according to externally applied additional replacement information.

Abstract: A semiconductor device comprising an active layer made from a crystalline silicon formed on a substrate having an insulating surface; a gate insulating film formed on said active layer; and a source region and a drain region provided in contact with said active layer; wherein, said active layer generates photo carriers upon irradiation of a light, a part of the thus generated photo carriers having the opposite polarity with respect to that of the carriers flowing in the vicinity of the interface with the gate insulating film is temporarily accumulated within said active layer to change the resistance of the region of said active layer, and the light irradiated to said active layer is detected from the change in current flow between the source and the drain which occurs in accordance with the change in resistance in the region of said active region.

Abstract: A semiconductor device testing method is disclosed which comprises a first process 39, a second process 41 and a third process 43. In the first process 39, a test function part of a semiconductor device having a built-in self-test function is subjected to a self-diagnostic test, and a main circuit part of the device in question is tested by its test function part. If the result of either of the two tests on the device turns out to be abnormal, the device in question is rejected as defective. The test results are saved. In the second process 41, the main circuit part of each semiconductor device rejected as defective in the first process 39 is tested by use of an external test signal. If the result of the test on the semiconductor device judged faulty in the first process 39 turns out to be normal in the second process 41, then the device in question is judged normal in the third process 43.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: An image display device having a plurality of pixcels with uniform light intensity comprises an organic EL element (3), a bias FET (2) for emit current control of said EL element, a capacitor (4) coupled with a gate electrode of said bias FET (2) for holding a signal, and a select FET (1) for selectively writing a signal to said capacitor (4), wherein the value S of said bias FET (2) is larger than that of said select FET (1).

Abstract: A thin film transistor which includes an insulation base, first and second gate electrodes, first and second insulation layers, an active layer of semiconductor material, a source electrode and a drain electrode, in which a lateral length of the first gate electrode is narrower than a lateral length of the second gate electrode. Also, the first gate is electrically insulated from the active layer of semiconductor material by the first insulation layer so that the drain current saturates in a high drain voltage region.

Abstract: A substrate (1) has a surface covered with an insulation layer (2), on which an active layer (3') made of non-single crystal silicon through thin film technique is provided. A gate electrode layer (5') is partially provided on said active layer through a gate insulation layer (4). Said active layer (3') is subject to injection of P-type or N-type impurities to provide an image sensor of MOS structure. Bias potential is applied to a gate electrode so that a circuit between a source and a drain is in an On state, so that input light through said substrate or said gate electrode is applied to said active layer, and electrical output depending upon said input light is obtained from said source electrode or said drain electrode. Other MOS transistors for switching element and/or shift registers for operating said image sensor are provided on said substrate (1).

Abstract: An image sensor (10) has a substrate (1), an active layer (3') having a source region and a drain region placed on said substrate (1), a gate insulation layer (4') placed on said active layer, and a gate electrode layer (5') on said gate insulation layer (4'). The active layer (3') is produced by the steps of producing amorphous silicon layer by using disilane gas (Si.sub.2 H.sub.6) through Low Pressure CVD process, and annealing said layer at 500.degree.-650.degree. C. for 4-50 hours in nitrogen gas atmosphere. The gate insulation layer (4') is produced through oxidation of the surface of the active layer at high temperature around 900.degree.-1100.degree. C. The oxidation process at high temperature improves the anneal process and improves the active layer. Thus, an image sensor with uniform characteristics is obtained with improved producing yield rate.