Patents by Inventor Kazushige Hotta
Kazushige Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7535065Abstract: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.Type: GrantFiled: December 29, 2004Date of Patent: May 19, 2009Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Publication number: 20080283840Abstract: The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.Type: ApplicationFiled: February 11, 2008Publication date: November 20, 2008Applicant: SHARP KABUSHIKI KAISHAInventors: Seiji Doi, Kazushige Hotta, Takuya Hirano, Kenichi Yanai
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Patent number: 7432138Abstract: A thin film transistor substrate is provided whose structure allows for the formation of (i) a thick gate insulating film, (ii) a high pressure resistance TFT having a LDD region of a GOLD structure, and (iii) a low voltage TFT having a thin gate insulating film, with less number of production steps.Type: GrantFiled: January 30, 2008Date of Patent: October 7, 2008Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Publication number: 20080191214Abstract: A method for manufacturing a thin film transistor substrate includes (a) a step of forming a plurality of island-like semiconductor films (13) above an insulating transparent substrate (10); (b) a step of forming a gate insulating film (21) on each of the island-like semiconductor films (13); (c) a step of forming first conductivity type LDD regions on both sides in the first island-like semiconductor film (13) by leaving a channel region and forming a first conductivity type normally-on channel region having an impurity density equivalent to that of the LDD region in the second island-like semiconductor film (13); (d) a step of forming a first gate electrode (32a) partially covering the LDD region and forming a second gate electrode (33a) above the normally-on channel region, and (e) a step of forming a first conductivity type source/drain region having an impurity density higher than that of the LDD region in regions on the both sides of the gate electrode.Type: ApplicationFiled: May 16, 2006Publication date: August 14, 2008Inventor: Kazushige Hotta
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Patent number: 7399662Abstract: A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and high-voltage driven thin film transistor formation regions. The method also includes forming a first insulating film on the first and second semiconductor films, and forming a first gate electrode on the first insulating film in the low-voltage driven thin film transistor formation region. Additionally, a second insulating film is formed on the entire surface of the resultant structure above the substrate, and a second gate electrode is formed on the second insulating film in the high-voltage driven thin film transistor formation region. The method also includes etching the first and second insulating films, thus forming first and second gate insulating films below, respectively, the first and second gate electrodes, with the second gate insulating film being wider than the second gate electrode.Type: GrantFiled: October 7, 2005Date of Patent: July 15, 2008Assignee: Sharp Kabushiki KaishaInventors: Ken-ichi Yanai, Yoshio Nagahiro, Kazushige Hotta, Koji Ohgata, Yasuyoshi Mishima, Nobuo Sasaki
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Publication number: 20080132010Abstract: A thin film transistor substrate is provided whose structure allows for the formation of (i) a thick gate insulating film, (ii) a high pressure resistance TFT having a LDD region of a GOLD structure, and (iii) a low voltage TFT having a thin gate insulating film, with less number of production steps.Type: ApplicationFiled: January 30, 2008Publication date: June 5, 2008Applicant: SHARP KABUSHIKI KAISHAInventor: Kazushige HOTTA
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Patent number: 7348631Abstract: A thin film transistor substrate is provided whose structure allows for the formation of (i) a thick gate insulating film, (ii) a high pressure resistance TFT having a LDD region of a GOLD structure, and (iii) a low voltage TFT having a thin gate insulating film, with less number of production steps.Type: GrantFiled: May 26, 2006Date of Patent: March 25, 2008Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Patent number: 7344930Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration-source/drain regions provided between the channel regions and the n-type high-concentration source/drain regiType: GrantFiled: April 25, 2007Date of Patent: March 18, 2008Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Patent number: 7323351Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: July 18, 2005Date of Patent: January 29, 2008Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
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Patent number: 7317209Abstract: In a method for manufacturing a TFT device, a metal thin film is formed on a gate insulation film. Patterning is performed to remove the metal thin film on a semiconductor layer, and phosphorous ions are implanted using the patterned metal thin film as a mask to form the source and drain regions. The patterned metal thin film is further patterned to form a gate electrode of an n-type TFT. Phosphorous ions are implanted using the gate electrode as a mask to form LDD regions between the source and drain regions and a channel region.Type: GrantFiled: July 2, 2003Date of Patent: January 8, 2008Assignee: Sharp Kabushiki KaishaInventors: Yoshio Kurosawa, Kazushige Hotta
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Patent number: 7291862Abstract: A method for producing a thin film transistor substrate includes the steps of: (i) depositing an amorphous semiconductor film on a transparent insulating substrate; (ii) patterning the amorphous semiconductor film so as to form insular amorphous semiconductor films, the step (ii) including a process (I) for forming, in respective stripe areas each of which is elongate in a first direction in a display area, a plurality of insular semiconductor films whose channel length is in line with the first direction, and a process (II) for forming, in an area including extended portions of the striped areas in a peripheral circuit area, a plurality of insular semiconductor films; (iii) polycrystallizing the insular semiconductor films in the peripheral circuit area so that the insular semiconductor films have high mobility in a second direction and polycrystallizing the insular semiconductor films in the display area so that the insular semiconductor films have high mobility in the first direction; and (iv) forming TFTsType: GrantFiled: March 21, 2006Date of Patent: November 6, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Takuya Hirano
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Patent number: 7279348Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: July 18, 2005Date of Patent: October 9, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
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Publication number: 20070205415Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration-source/drain regions provided between the channel regions and the n-type high-concentration source/drain regiType: ApplicationFiled: April 25, 2007Publication date: September 6, 2007Applicant: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Patent number: 7256457Abstract: A TFT device, a method of manufacturing the same, a TFT substrate and a display device, making it possible to decrease the photolithography steps, to improve the productivity and to decrease the cost of production. There are formed on the same substrate a first n-ch TFT having an LDD region which is entirely covered with a gate electrode, a second n-ch TFT having an LDD region partially covered with a gate electrode, and a p-ch TFT. Here, electrically conducting thin films and a gate electrode are formed on the electrically conducting thin film and on the insulating film, phosphorus ions are implanted into source/drain regions of the n-ch TFTs using the electrically conducting thin films and gate electrode as masks, and a gate electrode is formed by etching the electrically conducting thin film by using the electrically conducting thin film as a mask.Type: GrantFiled: September 15, 2004Date of Patent: August 14, 2007Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Patent number: 7227187Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration source/drain regions provided between the channel regions and the n-type high-concentration source/drain regiType: GrantFiled: October 17, 2005Date of Patent: June 5, 2007Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Publication number: 20070111411Abstract: A thin film transistor substrate is provided whose structure allows for the formation of (i) a thick gate insulating film, (ii) a high pressure resistance TFT having a LDD region of a GOLD structure, and (iii) a low voltage TFT having a thin gate insulating film, with less number of production steps.Type: ApplicationFiled: May 26, 2006Publication date: May 17, 2007Applicant: SHARP KABUSHIKI KAISHAInventor: Kazushige Hotta
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Patent number: 7189603Abstract: A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is fomed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold voltage for p-channel TFT. A second gate electrode layer is formed and patterned to form second gate electrodes. By using the first gate electrode layer as a mask, boron ions are implanted at a high concentration to form source/drain regions of the p-channel TFT. By using the second gate electrodes as a mask, the first gate electrode layer is etched to form gate electrodes. Phosphorous ions are implanted at a low concentration to form LDD regions. By using a fourth mask, P ions are implanted at a high concentration to form source/drain regions of n-channel TFTs.Type: GrantFiled: September 14, 2005Date of Patent: March 13, 2007Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Patent number: 7161181Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: July 18, 2005Date of Patent: January 9, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
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Publication number: 20060289870Abstract: A method for producing a thin film transistor substrate includes the steps of: (i) depositing an amorphous semiconductor film on a transparent insulating substrate; (ii) patterning the amorphous semiconductor film so as to form insular amorphous semiconductor films, the step (ii) including a process (I) for forming, in respective stripe areas each of which is elongate in a first direction in a display area, a plurality of insular semiconductor films whose channel length is in line with the first direction, and a process (II) for forming, in an area including extended portions of the striped areas in a peripheral circuit area, a plurality of insular semiconductor films; (iii) polycrystallizing the insular semiconductor films in the peripheral circuit area so that the insular semiconductor films have high mobility in a second direction and polycrystallizing the insular semiconductor films in the display area so that the insular semiconductor films have high mobility in the first direction; and (iv) forming TFTsType: ApplicationFiled: March 21, 2006Publication date: December 28, 2006Inventors: Kazushige Hotta, Takuya Hirano
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Patent number: 7038283Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.Type: GrantFiled: March 22, 2002Date of Patent: May 2, 2006Assignee: Fujitsu Display Technologies CorporationInventors: Kenichi Yanai, Yoshio Nagahiro, Kazushige Hotta, Koji Ohgata, Yasuyoshi Mishima, Nobuo Sasaki