Abstract: A nonvolatile semiconductor memory device includes a memory string that includes a plurality of first memory cells, a plurality of second memory cells, and a transistor electrically connected between the plurality of first memory cells and the plurality of second memory cells, and a control circuit that performs a program operation by applying a program voltage to a gate of a selected first memory cell among the plurality of first memory cells and a gate of a selected second memory cell among the plurality of second memory cells, a pass voltage lower than the program voltage to other memory cells in the plurality of first and second memory cells, and a control voltage to a gate of the transistor.

Abstract: A semiconductor memory device includes a bit line, an active region formed in a semiconductor substrate, a plug formed on the active region and connecting the bit line to the active region, a memory cell which includes a first gate insulating film on the active region, a charge storage layer on the first gate insulating film, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, a select transistor formed between the plug and the memory cell on the active region and including a second gate insulating film on the active region, a first electrode layer on the second gate insulating film, a second insulating film on the first electrode layer, and a second electrode layer on the second insulating film, and a wiring formed above the active region between the plug and the second electrode layer of the select transistor.

Abstract: A semiconductor memory device includes a bit line, an active region formed in a semiconductor substrate, a plug formed on the active region and connecting the bit line to the active region, a memory cell which includes a first gate insulating film on the active region, a charge storage layer on the first gate insulating film, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, a select transistor formed between the plug and the memory cell on the active region and including a second gate insulating film on the active region, a first electrode layer on the second gate insulating film, a second insulating film on the first electrode layer, and a second electrode layer on the second insulating film, and a wiring formed above the active region between the plug and the second electrode layer of the select transistor.

Abstract: A semiconductor memory device is provided, including a memory cell array having a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output.

Abstract: According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.

Abstract: Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to conn

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells. The control circuit tests the diode at least at one of times before and after one of a write operation, erase operation and read operation with respect to the memory cell is performed.

Abstract: A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

Abstract: According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well.

Abstract: A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on circuits capable of being reset. The selection information is externally input. The reset control circuit outputs a reset signal on the basis of the selection information held in the latch circuit in response to a power-on reset signal and the first trigger signal output from the reset sequence circuit.

Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.

Abstract: According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.

Abstract: According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array which comprises a plurality of blocks each comprising a plurality of memory cells, ordinary data being stored in ordinary blocks included in the plurality of blocks, a time code which is set for each of the ordinary blocks and which comprises time data corresponding to time when a last write operation into the ordinary block is executed being stored in a time code block included in the plurality of blocks. The time code is read out from the time code block, current time is acquired, with respect to selected one of the ordinary blocks for which a time difference between time in the time code read out and the current time becomes greater than a prescribed value, data is read and erased and the data read out is written, and a new time code corresponding to time data of the current time is written into the time code block in association with the selected ordinary block.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output.

Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.

Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.

Abstract: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.