Abstract: A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit.

Abstract: The booster circuit of the present invention includes a first booster cell section in which one or more booster cells are connected in series, and a second booster cell section having an end which is connected to the first booster cell section, in which a plurality of booster cell groups each containing one or more booster cells connected in series, are connected to each other in parallel.

Abstract: A semiconductor integrated circuit includes the reference current generating circuit free from both the influence of a power supply voltage and the influence of the variation of the threshold voltage of the transistors related to the generation of the reference current. In the reference current generating circuit, a P-channel MOS transistor (Qp1), a N-channel MOS transistor (Qn1), a resistor element (R1), and a N-channel MOS transistor (Qn2) are connected in series between the power supply voltage and the ground. The gate and the drain of the N-channel MOS transistor (Qn2) are connected by a short circuit to output the reference current Iref from a transistor (Qn6) through the resistor element.

Abstract: An internal address signal generation circuit generates an internal address signal necessary for accessing a memory cell array. A defective address storage circuit stores a defective address signal of the memory cell array. A first comparison circuit compares the internal address signal and defective address signal. A latch circuit latches a redundant testing address signal supplied from outside. A second comparison circuit compares the redundant testing address signal and the internal address signal. A selection circuit selects an output signal of the second comparison circuit in a redundant test mode. In response to the selected output signal, part of the memory cell array is replaced with a redundant memory cell array.

Abstract: An EEPROM employs, as a scheme of detecting data of a memory cell in a memory cell array, a scheme of detecting the potential of a bit line potential sense node, which depends on the relationship in amplitude between the current for charging a bit line from a current source and the discharge current flowing to a selected cell using a sense amplifier. The sense amplifier is arranged in correspondence with one bit line and includes a constant current source transistor for charging the corresponding bit line, a latch circuit for latching memory cell data read out to the bit line potential sense node, and a switch transistor for turning on/off the charge path to the bit line based on data of the latch circuit. In the verify read mode, the cell current between the Vcc node and Vss node of a cell not to be written or a completely written cell can be turned off, so verification can be performed without flowing any unnecessary current.