Patents by Inventor Kazushige Sato
Kazushige Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040203199Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: ApplicationFiled: April 29, 2004Publication date: October 14, 2004Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 6747324Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETS and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: GrantFiled: June 16, 2003Date of Patent: June 8, 2004Assignee: Hitachi, Ltd.Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 6661063Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: GrantFiled: March 2, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Publication number: 20030205766Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: ApplicationFiled: June 16, 2003Publication date: November 6, 2003Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 6603178Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: GrantFiled: January 4, 2001Date of Patent: August 5, 2003Assignee: Hitachi, Ltd.Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Publication number: 20030122159Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes;of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.Type: ApplicationFiled: November 26, 2002Publication date: July 3, 2003Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya lida, Akihiro Shimizu
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Patent number: 6548885Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: January 8, 2001Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 6544884Abstract: A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5<A<2.78−1.02B+0.172B2.Type: GrantFiled: December 20, 2001Date of Patent: April 8, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Ohta, Hideo Miura, Kazushige Sato, Takeshi Kimura, Hiyoo Masuda
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Publication number: 20020043724Abstract: A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5<A<2.78−1.02B+0.172B2.Type: ApplicationFiled: December 20, 2001Publication date: April 18, 2002Inventors: Hiroyuki Ohta, Hideo Miura, Kazushige Sato, Takeshi Kimura, Hiyoo Masuda
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Patent number: 6337517Abstract: A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5<A<2.78−1.02B+0.172B2.Type: GrantFiled: September 11, 1998Date of Patent: January 8, 2002Assignee: Hitachi, Ltd.Inventors: Hiroyuki Ohta, Hideo Miura, Kazushige Sato, Takeshi Kimura, Hiroo Masuda
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Publication number: 20010050399Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: ApplicationFiled: March 2, 2001Publication date: December 13, 2001Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Publication number: 20010019641Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.Type: ApplicationFiled: January 8, 2001Publication date: September 6, 2001Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20010001718Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: ApplicationFiled: January 4, 2001Publication date: May 24, 2001Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 6211004Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: June 16, 1999Date of Patent: April 3, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 6171892Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: GrantFiled: February 18, 1998Date of Patent: January 9, 2001Assignee: Hitachi, Ltd.Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 5946565Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: June 23, 1997Date of Patent: August 31, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 5798551Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: GrantFiled: January 17, 1997Date of Patent: August 25, 1998Assignee: Hitachi, Ltd.Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 5754467Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.Type: GrantFiled: May 25, 1995Date of Patent: May 19, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 5607866Abstract: In a method of fabricating a semiconductor device having a MISFET and/or bipolar transistor and/or a resistor formed with different surface portions of a single silicon semiconductor substrate in which a silicide layer is formed on each of source/drain regions of the MISFET and/or collector contact region and extrinsic base region of the bipolar transistor and/or contact regions of the resistor, the bipolar transistor has its emitter region formed by diffusing an impurity contained in doped polysilicon film serving as an emitter electrode of the bipolar transistor into a part of its base region. The resistor may have a resistive region formed in a surface portion of the substrate and may be covered with an insulating film and a doped polysilicon film thereon or may have a doped polysilicon film formed over a surface portion of the substrate as a resistor element.Type: GrantFiled: June 2, 1995Date of Patent: March 4, 1997Assignee: Hitachi, Ltd.Inventors: Kazushige Sato, Atsuo Watanabe, Kenichi Kikushima, Nobuo Owada, Masaya Iida
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Patent number: 5523598Abstract: The gate electrodes of the driver MISFETs, transfer MISFETs and load MISFETS of the static random access memory (SRAM) are formed of the first-level conductive layer deposited over the main surface of the semiconductor substrate. The gate electrodes, power source voltage line, reference voltage line, local interconnection lines, and complementary data lines, all making up the conductive layers of the SRAM memory cell, are formed of different conductive layers, i.e. conductive layers of different levels. The local interconnection lines and the reference voltage line or power source voltage line are arranged, with respect to a plan view of the main surface of the substrate, to cross each other and a capacitance is formed in the intersecting regions.Type: GrantFiled: June 14, 1994Date of Patent: June 4, 1996Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Kazushige Sato