Patents by Inventor Kazushige Takaishi
Kazushige Takaishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100237470Abstract: An epitaxial wafer is provided capable of eliminating particles in a device process, particles being generated from scratches in a boundary area between a rear surface and a chamfered surface of a wafer. The number of scratches in the boundary area between the rear surface and the chamfered surface is small, and thus the number of particles generated from the scratches is reduced at a time of immersion in an etching solution in the device process. Thereby, a device yield is increased.Type: ApplicationFiled: November 6, 2008Publication date: September 23, 2010Applicant: SUMCO CORPORATIONInventors: Kazushige Takaishi, Tomonori Miura
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Publication number: 20100151597Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.Type: ApplicationFiled: January 17, 2007Publication date: June 17, 2010Applicant: SUMCO CORPORATIONInventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
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Patent number: 7717768Abstract: This wafer polishing apparatus includes: a polishing plate having a polishing pad; a carrier plate which is placed facing the polishing pad and which slides and presses wafers against the polishing pad, while rotating in a state of holding the wafers; and an abrasive slurry supply device, wherein the abrasive slurry supply device is able to supply different abrasive slurries, each of the abrasive slurries contains abrasives of which the average grain size is different from those contained in the other abrasive slurries. This method for polishing wafers includes: while supplying an abrasive slurry to a surface of a polishing pad, sliding and pressing wafers against the polishing pad, wherein different abrasive slurries are supplied to the surface of the polishing pad, and each of the abrasive slurries contains abrasives of which the average grain size is different from those contained in the other abrasive slurries.Type: GrantFiled: May 11, 2006Date of Patent: May 18, 2010Assignee: Sumco CorporationInventors: Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
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Publication number: 20100032806Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.Type: ApplicationFiled: July 20, 2009Publication date: February 11, 2010Applicant: SUMCO CORPORATIONInventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
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Publication number: 20100021688Abstract: A wafer manufacturing method includes after flattening both upper and lower surfaces of a wafer sliced from a single crystal ingot, processing the wafer having damage on both surfaces caused by the flattening, so as to obtain desired damage at least on the lower surface of the wafer, the desired damage having a damage depth ranging from 5 nm-10 ?m; forming a polysilicon layer at least on the lower surface of the wafer while the damage on the lower surface of the wafer remains; single-wafer etching the upper surface of the wafer; and final polishing the upper surface of the wafer to have a mirrored surface, after the single-wafer etching.Type: ApplicationFiled: July 21, 2009Publication date: January 28, 2010Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Tomohiro HASHII, Katsuhiko MURAYAMA, Sakae KOYATA, Kazushige TAKAISHI
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Patent number: 7648890Abstract: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching solution over all the surface of the wafer; and a grinding step of grinding the surface of the wafer, in this order, wherein the etching solution used in the single-wafer etching step is an aqueous acid solution which contains hydrogen fluoride, nitric acid, and phosphoric acid in an amount such that the content of which by weight % at a mixing rate of fluoric acid:nitric acid:phosphoric acid is 0.5 to 40%:5 to 50%:5 to 70%, respectively.Type: GrantFiled: August 15, 2006Date of Patent: January 19, 2010Assignee: Sumco CorporationInventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
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Publication number: 20100009155Abstract: It is to provide a double-side mirror-finished semiconductor wafer having an excellent flatness by conducting a polishing step from rough polishing to finish polishing for simultaneously polishing both surfaces of a raw wafer with the same polishing cloth to reduce the polishing amount of the raw wafer as well as a production method thereof.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: Sumco CorporationInventors: Tomohiro Hashii, Kazushige Takaishi
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Publication number: 20100006982Abstract: There is provided a method of producing a semiconductor wafer which is high in the beveling accuracy and the yield for large-size wafers having a diameter of not less than 450 mm, comprising a slicing step for cutting out a disc-shaped wafer having a diameter of not less than 450 mm from a single crystal ingot, a step for lapping a surface of the wafer to conduct planarization, a step for beveling an edge portion of the wafer, a step for grinding the surface of the wafer and a step for mirror-polishing the surface of the wafer, wherein the planarizing step performs the lapping with free abrasive grains of #1000 to #1500.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: Sumco CorporationInventors: Tomohiro Hashii, Kazushige Takaishi
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Patent number: 7645702Abstract: The manufacturing method of the present invention provides a silicon wafer, both sides of the wafer having a highly accurate flatness and small surface roughness, which is a single surface mirror-polished wafer with the front and rear surfaces of the wafer identifiable by visual observation, and excellent in flatness when held by a stepper chuck and the like. The manufacturing method of the present invention includes an etching process, a lapping process, and a double surface polishing process to simultaneously polish the front and rear surfaces of a wafer after the etching process. The polishing removal depth (A) of the wafer front surface is 5 to 10 ?m in the double surface simultaneous polishing process, and the polishing removal depth (B) in the rear surface is 2 to 6 ?m, and a difference between the polishing removal depth A and the polishing removal depth B is 3 to 4 ?m.Type: GrantFiled: October 28, 2004Date of Patent: January 12, 2010Assignee: SUMCO CorporationInventors: Sakae Koyata, Kazushige Takaishi
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Publication number: 20090311460Abstract: A semiconductor wafer with high flatness is provided. The semiconductor wafer has a diameter ? of 450 mm and a thickness of at least 900 ?m and no greater than 1,100 ?m.Type: ApplicationFiled: June 5, 2009Publication date: December 17, 2009Applicants: SUMCO CORPORATION, SUMCO TECHXIV CORPORATIONInventors: Tomohiro HASHII, Kazushige TAKAISHI, Shinji SAKAMOTO, Tomoko OHMACHI
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Publication number: 20090304975Abstract: An epitaxial silicon wafer in which on growing an epitaxial film only on the front side of a large-sized wafer which is 450 mm or more in diameter, the wafer can be decreased in warpage to obtain a high intrinsic gettering performance and a method for producing the epitaxial silicon wafer. Intrinsic gettering functions have been imparted to a high resistant large-sized silicon wafer which is 450 mm or more in diameter and 0.1 ?·cm or more in specific resistance by introducing nitrogen, carbon or both of them to a melt on pulling up an ingot. Thereby, after the growth of an epitaxial film, a silicon wafer is less likely to warp greatly. As a result, it is possible to decrease the warpage of an epitaxial silicon wafer and also to obtain a high intrinsic gettering performance.Type: ApplicationFiled: June 4, 2009Publication date: December 10, 2009Applicant: SUMCO CORPORATIONInventors: Seiji SUGIMOTO, Kazushige TAKAISHI
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Publication number: 20090304490Abstract: The present invention is directed to provide a method for holding a silicon wafer, which can reduce contact scratches in contact with support members when holding a back surface of the silicon wafer, as well as prevent the wafer from bending when holding the back surface of the silicon wafer. The back surface of a silicon wafer of 300 millimeters or more in diameter and 700 micrometers to 1000 micrometers in thickness is held in contact with a support member or a suction member, specifically held within a region where a radius of the silicon wafer×0.50 to 0.80 from a center thereof. The silicon wafer is held in a state where the maximum amount of displacement within a wafer plane is 300 micrometers or less. The silicon wafer back surface is held in contact within the holding region in all the processes of holding the back surface of the silicon wafer in contact with the support member or the suction member.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Inventors: Takayuki Kihara, Masataka Hourai, Yuki Murata, Kazushige Takaishi, Seiji Sugimoto, Tadashi Kanda
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Publication number: 20090298397Abstract: A method of grinding semiconductor wafers including simultaneously grinding both surfaces of multiple semiconductor wafers being ground by rotating the multiple semiconductor wafers between a pair of upper and lower rotating surface plates in a state where the multiple wafers are held on a carrier so that centers of the multiple wafers are positioned on a circumference of a single circle, wherein a ratio of an area of a circle passing through the centers of the multiple wafers to an area of one of the multiple wafers is greater than or equal to 1.33 but less than 2.0; a rotational speed of the multiple wafers falls within a range of 5 to 80 rpm; and the grinding of the multiple wafers with the rotating surface plates are conducted with fixed abrasive grains in the presence of an alkali solution.Type: ApplicationFiled: May 22, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Yasunori YAMADA, Yuichi KAKIZONO, Kazushige TAKAISHI
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Publication number: 20090297867Abstract: An adhesive agent high in thixotropy is coated on the flat surface of a circular glass substrate in a uniform thickness, a silicon wafer equal in diameter is placed thereon, the adhesive agent is cured, and the silicon wafer is pasted together on the glass substrate.Type: ApplicationFiled: June 2, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI
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Publication number: 20090293919Abstract: A semiconductor wafer is cleaned by supplying a given cleaning solution to a central position of a front surface and/or a back surface of a semiconductor wafer while rotating the wafer, wherein the cleaning is conducted so as to form a water film having a thickness of 5-10 ?m on a whole surface of the wafer with the cleaning solution.Type: ApplicationFiled: May 29, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo Katoh, Kazushige Takaishi, Ryuichi Tanimoto
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Publication number: 20090298394Abstract: A silicon wafer is polished by applying a polishing solution substantially containing no abrasive grain onto a surface of a polishing pad having a given fixed grain bonded abrasive and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, wherein a hydroplane layer is formed by the polishing solution supplied between the surface of the silicon wafer and the surface of the polishing pad and a thickness of the hydroplane layer is controlled to change a polishing state of the surface of the silicon wafer.Type: ApplicationFiled: May 27, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo Katoh, Ryuichi Tanimoto, Shinichi Ogata, Takeru Takushima, Kazushige Takaishi
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Publication number: 20090294910Abstract: A reinforcement member made with silicon carbide different from silicon is installed on the back face of a silicon wafer, thereby the silicon wafer is increased in Young's modulus and the wafer is less likely to deflect.Type: ApplicationFiled: June 2, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI
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Publication number: 20090294918Abstract: In a state where a semiconductor wafer is not acted upon by its own weight, a shear stress on a rear surface side portion of the semiconductor wafer is higher than that on a front surface side portion of the semiconductor wafer, in a compression direction. Thereby, sag of the semiconductor wafer is reduced when the semiconductor wafer is simple-supported in a horizontal state.Type: ApplicationFiled: June 1, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI
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Publication number: 20090297426Abstract: When a monocrystal is pulled up, an additive element such as boron is added to a molten silicon, and a pulling-up condition is such that a solid solution oxygen concentration is equal to or higher than 2×1018 atoms/cm3 and a chemical compound precipitation area of silicon and the additive element is formed.Type: ApplicationFiled: June 1, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI
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Patent number: 7601642Abstract: The inventive method for processing a silicon wafer is a method comprising step 11 in which a single crystal ingot is sliced into thin disc-like wafers; step 13 in which the surface of each wafer is lapped to be planar; step 14 in which the wafer is subjected to alkaline cleaning to be removed of contaminants resulting from preceding machining; and step 16 in which the wafer is alternately transferred between two groups of etching tanks one of which contain acidic etching solutions and the other alkaline etching solutions, wherein an additional step 12 is introduced between step 11 and step 13 in which a wafer is immersed in an acidic solution containing hydrofluoric acid (HF) and nitric acid (HNO3) at a volume ratio of ? to ½ (HF/HNO3) so that degraded superficial layers occurring on the front and rear surfaces of the wafer as a result of machining can be removed and the edge surface of the wafer can be beveled.Type: GrantFiled: May 27, 2004Date of Patent: October 13, 2009Assignee: Sumco CorporationInventors: Sakae Koyata, Kazushige Takaishi