Patents by Inventor Kazutaka Akiyama

Kazutaka Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8580652
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 8415750
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; an element isolation insulating film embedded in the vicinity of a front surface of the semiconductor substrate; a through plug penetrating the semiconductor substrate from a back surface to the front surface so as to penetrate through the element isolation insulating film, and having a multi-stage structure comprising an upper stage portion and a lower stage portion, the upper stage portion having a region surrounded by the element isolation insulating film in the semiconductor substrate, the lower stage portion having a diameter larger than that of the upper stage portion; and a contact plug connected to an end portion of the through plug on the frond surface side of the semiconductor substrate for connecting a conductive member formed above the front surface side of the semiconductor substrate to the through plug.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: April 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 8008779
    Abstract: Disclosed is a semiconductor device that includes: a semiconductor substrate; a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less; a conductor which covers a side face of the first insulating film at least near four corners of the semiconductor substrate, and at least an outer side face of which has a conductive barrier layer; and a second insulating film covering the outer side face of the conductor and having a relative dielectric constant of over 3.8. Also disclosed is a semiconductor device that includes: a conductor covering a side face of the first insulating film at least near four corners of the semiconductor substrate; and a corrosion resistant conductor formed at least near the four corners of the semiconductor substrate to extend from directly under the second insulating film to directly under the conductor.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Publication number: 20110163453
    Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.
    Type: Application
    Filed: March 11, 2011
    Publication date: July 7, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 7943459
    Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Akiyama, Takaya Matsushita
  • Patent number: 7919835
    Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Publication number: 20110068476
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 24, 2011
    Inventors: Atsuko KAWASAKI, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 7888760
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Sugiyama, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
  • Publication number: 20110024849
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; an element isolation insulating film embedded in the vicinity of a front surface of the semiconductor substrate; a through plug penetrating the semiconductor substrate from a back surface to the front surface so as to penetrate through the element isolation insulating film, and having a multi-stage structure comprising an upper stage portion and a lower stage portion, the upper stage portion having a region surrounded by the element isolation insulating film in the semiconductor substrate, the lower stage portion having a diameter larger than that of the upper stage portion; and a contact plug connected to an end portion of the through plug on the frond surface side of the semiconductor substrate for connecting a conductive member formed above the front surface side of the semiconductor substrate to the through plug.
    Type: Application
    Filed: January 11, 2010
    Publication date: February 3, 2011
    Inventor: Kazutaka AKIYAMA
  • Patent number: 7831330
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Publication number: 20100102454
    Abstract: When an etch stopper film is stacked on a pad electrode in which an opening is provided and a through electrode is embedded in a through hole formed in a semiconductor substrate, a distal end of the through electrode penetrates a part of the pad electrode via the opening and is stopped by the etch stopper film.
    Type: Application
    Filed: July 6, 2009
    Publication date: April 29, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka AKIYAMA
  • Patent number: 7701004
    Abstract: A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the second conductive layer. An interlayer insulator has a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on the first layered film. The interlayer insulator is formed covering the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: April 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Publication number: 20090276078
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Application
    Filed: July 10, 2009
    Publication date: November 5, 2009
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7611994
    Abstract: An insulation film is formed on a semiconductor substrate. A stopper film, which has a large etching selectivity relative to the insulation film and has a first film thickness, is formed on the insulation film. A first mask material, which has a second film thickness that is less than the first film thickness, is formed on the stopper film. A first mask is formed by patterning the first mask material. An opening portion is formed by etching the stopper film using the first mask. The opening portion is filled with a second mask material. A second mask of the second mask material is formed by removing the stopper film. The insulation film is etched using the second mask.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 7596421
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: September 29, 2009
    Assignee: Kabushik Kaisha Toshiba
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Publication number: 20090152602
    Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 18, 2009
    Inventor: Kazutaka AKIYAMA
  • Publication number: 20090096051
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hitoshi SUGIYAMA, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
  • Publication number: 20080211030
    Abstract: A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the second conductive layer. An interlayer insulator has a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on the first layered film. The interlayer insulator is formed covering the first conductive layer and the second conductive layer.
    Type: Application
    Filed: January 31, 2008
    Publication date: September 4, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 7348623
    Abstract: A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cover the MIM capacitor; a second wiring formed on the second insulating film; and a guard ring buried in the second insulating film to surround the MIM capacitor.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: March 25, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Publication number: 20080054395
    Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.
    Type: Application
    Filed: August 24, 2007
    Publication date: March 6, 2008
    Inventors: Kazutaka Akiyama, Takaya Matsushita