Patents by Inventor Kazutaka Akiyama

Kazutaka Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070013076
    Abstract: A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the second conductive layer. An interlayer insulator has a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on the first layered film. The interlayer insulator is formed covering the first conductive layer and the second conductive layer.
    Type: Application
    Filed: May 18, 2006
    Publication date: January 18, 2007
    Inventor: Kazutaka Akiyama
  • Publication number: 20060287754
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 21, 2006
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Publication number: 20060240639
    Abstract: An insulation film is formed on a semiconductor substrate. A stopper film, which has a large etching selectivity relative to the insulation film and has a first film thickness, is formed on the insulation film. A first mask material, which has a second film thickness that is less than the first film thickness, is formed on the stopper film. A first mask is formed by patterning the first mask material. An opening portion is formed by etching the stopper film using the first mask. The opening portion is filled with a second mask material. A second mask of the second mask material is formed by removing the stopper film. The insulation film is etched using the second mask.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 26, 2006
    Inventor: Kazutaka Akiyama
  • Publication number: 20060225651
    Abstract: An apparatus for manufacturing a semiconductor device includes: a process chamber configured to contain a substrate having an insulation film; a heating unit configured to degas the substrate; a gas monitor configured to monitor an amount of gas released from the insulation film; a controller configured to control the heating unit to stop the degassing, by determining an endpoint of the degassing using the monitored amount of the released gas; and a film deposition unit configured to deposit a metal film on the insulation film.
    Type: Application
    Filed: February 15, 2006
    Publication date: October 12, 2006
    Inventors: Koji Ueno, Kazutaka Akiyama
  • Publication number: 20050145986
    Abstract: A semiconductor device according to an aspect of this invention comprises a first lower interconnection formed on an insulating film on a semiconductor substrate, a first via formed on the first lower interconnection, and an MIM capacitor formed on the first via, and including a lower electrode, capacitor insulating film, and upper electrode.
    Type: Application
    Filed: November 12, 2004
    Publication date: July 7, 2005
    Inventor: Kazutaka Akiyama
  • Publication number: 20050145988
    Abstract: A semiconductor device includes a semiconductor substrate, an insulative film formed above the semiconductor substrate, the film having a first groove and a second groove greater in width than the first groove, a wiring lead buried in the first groove of the insulative film to have a substantially flat surface, and a capacitor buried in the second groove of the insulative film to have a substantially flat surface, the capacitor having a multilayer structure including a first conductive film identical in material to the lead, a capacitor dielectric film, and a second conductive film.
    Type: Application
    Filed: February 16, 2005
    Publication date: July 7, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 6909188
    Abstract: There is disclosed a semiconductor device comprising a first wire and a pad portion thereof provided in a portion from an upper surface to an inner portion of a first insulation film provided above a substrate, a second insulation film provided on the first insulation film and the first wire, a second wire provided to be exposed from an upper surface of the second insulation film in an upper portion of the pad portion of the first wire, and a contact plug provided to reach an inner portion of the pad portion of the first wire from an undersurface of the second wire.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: June 21, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Publication number: 20050116333
    Abstract: Disclosed is a semiconductor device that includes: a semiconductor substrate; a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less; a conductor which covers a side face of the first insulating film at least near four corners of the semiconductor substrate, and at least an outer side face of which has a conductive barrier layer; and a second insulating film covering the outer side face of the conductor and having a relative dielectric constant of over 3.8. Also disclosed is a semiconductor device that includes: a conductor covering a side face of the first insulating film at least near four corners of the semiconductor substrate; and a corrosion resistant conductor formed at least near the four corners of the semiconductor substrate to extend from directly under the second insulating film to directly under the conductor.
    Type: Application
    Filed: March 24, 2004
    Publication date: June 2, 2005
    Inventor: Kazutaka Akiyama
  • Patent number: 6888220
    Abstract: A semiconductor device includes a semiconductor substrate, an insulative film formed above the semiconductor substrate, the film having a first groove and a second groove greater in width than the first groove, a wiring lead buried in the first groove of the insulative film to have a substantially flat surface, and a capacitor buried in the second groove of the insulative film to have a substantially flat surface, the capacitor having a multilayer structure including a first conductive film identical in material to the lead, a capacitor dielectric film, and a second conductive film.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: May 3, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Publication number: 20050006771
    Abstract: A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cover the MIM capacitor; a second wiring formed on the second insulating film; and a guard ring buried in the second insulating film to surround the MIM capacitor.
    Type: Application
    Filed: September 9, 2003
    Publication date: January 13, 2005
    Inventor: Kazutaka Akiyama
  • Publication number: 20040135267
    Abstract: There is disclosed a semiconductor device comprising a first wire and a pad portion thereof provided in a portion from an upper surface to an inner portion of a first insulation film provided above a substrate, a second insulation film provided on the first insulation film and the first wire, a second wire provided to be exposed from an upper surface of the second insulation film in an upper portion of the pad portion of the first wire, and a contact plug provided to reach an inner portion of the pad portion of the first wire from an undersurface of the second wire.
    Type: Application
    Filed: October 23, 2003
    Publication date: July 15, 2004
    Inventor: Kazutaka Akiyama
  • Publication number: 20030057558
    Abstract: A semiconductor device includes a semiconductor substrate, an insulative film formed above the semiconductor substrate, the film having a first groove and a second groove greater in width than the first groove, a wiring lead buried in the first groove of the insulative film to have a substantially flat surface, and a capacitor buried in the second groove of the insulative film to have a substantially flat surface, the capacitor having a multilayer structure including a first conductive film identical in material to the lead, a capacitor dielectric film, and a second conductive film.
    Type: Application
    Filed: September 11, 2002
    Publication date: March 27, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 5698336
    Abstract: A magnetic recording medium is disclosed, which has a magnetic layer containing a hexagonal ferrite powder dispersed in a resin binder, the magnetic layer being formed on a nonmagnetic supporting substrate, wherein the hexagonal ferrite powder is a compound represented by the following chemical formulaAO.2 (M.sup.1 0).Fe.sub.16-x M.sup.2.sub.x 0.sub.24where A is at least one element selected from the group consisting of Ba, Sr, Ca, and Pb; M.sup.1 is at least one element selected from the group consisting of Zn, Ni and Co; M.sup.2 is one combination selected from the group consisting of a combination of two elements of Co and Ti, a combination of two elements of Ti and Zn, and a combination of three elements of Co, Ti and Zn; and x designates a number in the range from 0.6 to 3.0, the hexagonal ferrite powder having an average diameter/thickness ratio in the range from 2.0 to 5.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Hashimoto, Tatsumi Maeda, Masahiro Fukasawa, Kazutaka Akiyama, Tsutomu Tanaka