Abstract: A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.

Abstract: According to one embodiment, a magnetic memory apparatus includes a first stacked body and a controller. The first stacked body includes a first magnetic layer, a first counter magnetic layer, and a first intermediate layer placed between the first magnetic layer and the first counter magnetic layer. The first intermediate layer is nonmagnetic. The controller is electrically connected to the first magnetic layer and the first counter magnetic layer. The controller is configured to perform a first operation of supplying first pulse current to the first stacked body. The first pulse current includes a first constant-current period. A first electrical resistance value of the first stacked body before the supply of the first pulse current is different from a second electrical resistance value of the first stacked body after the supply of the first pulse current.

Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

Abstract: According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

Abstract: A resistance change type memory includes a variable resistance element connected between first and second bit lines and a write control circuit including first and second transistors each including a terminal connected to the first bit line. The write control circuit controls write to the variable resistance element. The write control circuit supplies a second voltage to the first bit line with a first pulse width via the second transistor in the ON state after supplying a first voltage to the first bit line via the first transistor.

Abstract: According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

Abstract: According to one embodiment, a magnetic device includes: a first conductive layer; a first magnetoresistive effect element disposed on the first S conductive layer and including a first control terminal; and a first circuit configured to supply a first current in a first direction into the first conductive layer and apply a first control voltage to the first control terminal of the first magnetoresistive effect element, wherein in a case in which the first current is supplied to the first conductive layer, the first magnetoresistive effect element holds a value corresponding to a logical disjunction between a first value of first data in the first magnetoresistive effect element and a second value of the first control voltage corresponding to second data.

Abstract: A memory device according to an embodiment includes: a plurality of memory cells including a storage element having a first and second terminals; a reference resistor having a third and fourth terminals; a first current source electrically connected to the first terminal of the storage element in the selected memory cell; a second current source electrically connected to the third terminal; and a determination circuit that determines the greater one among a resistance value of a storage element of selected one and a resistance value of the reference resistor, the resistance value of the reference resistor being smaller than a middle value between a mean value of first resistance values obtained from the storage elements in the high-resistance state and a mean value of second resistance values obtained from the storage elements in the low-resistance state, and greater than the mean value of the second resistance values.

Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.

Abstract: According to one embodiment, a magnetic memory includes: a memory area; a first memory unit disposed in the memory area and including h first magnetoresistive effect elements arrayed on a first conductive layer; and a first circuit configured to receive i-bit first data, convert the first data into j-bit (j=h) second data, and write the second data in the first memory unit. The second data includes m first values and (j?m) second values, and m and j have a relationship given by “j/2?1?m?j/2+1”.

Abstract: A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.

Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.

Abstract: According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.

Abstract: A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data.

Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.

Abstract: A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.

Abstract: A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically connected to the first and second terminals respectively; a first magnetoresistive element including: a first and second magnetic layers; a first nonmagnetic layer between the first and second magnetic layers; and a third terminal electrically connected to the first magnetic layer; a second magnetoresistive element including: a third and fourth magnetic layers; a second nonmagnetic layer between the third and fourth magnetic layers; and a fourth terminal electrically connected to the third magnetic layer; and a circuit configured to apply a write current between the first terminal and the second terminal and apply a first and second potentials to the third and fourth terminals respectively to write the first and second magnetoresistive elements, the first and second potentials being different from each other.

Abstract: According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.

Abstract: A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.

Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.