Patents by Inventor Kazutaka Ikegami
Kazutaka Ikegami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8856199Abstract: A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.Type: GrantFiled: November 22, 2011Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tetsufumi Tanamoto, Mari Matsumoto, Shinobu Fujita, Kazutaka Ikegami
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Patent number: 8824199Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected.Type: GrantFiled: February 8, 2013Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Noguchi, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Kazutaka Ikegami
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Patent number: 8805907Abstract: It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured to receive an output of the current noise source; and a conversion circuit configured to convert output frequency fluctuation of the ring oscillator to a random number and output the random number.Type: GrantFiled: September 17, 2008Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazutaka Ikegami, Shinichi Yasuda
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Patent number: 8724403Abstract: According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.Type: GrantFiled: December 28, 2012Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Shinobu Fujita, Keiko Abe, Kazutaka Ikegami, Hiroki Noguchi
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Publication number: 20140104920Abstract: According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.Type: ApplicationFiled: October 1, 2013Publication date: April 17, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Hiroki Noguchi, Shinobu Fujita
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Patent number: 8650233Abstract: A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.Type: GrantFiled: September 23, 2008Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazutaka Ikegami, Shinichi Yasuda
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Publication number: 20130322161Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.Type: ApplicationFiled: February 21, 2013Publication date: December 5, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroki NOGUCHI, Keiko ABE, Kazutaka IKEGAMI, Shinobu FUJITA
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Publication number: 20130301345Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected.Type: ApplicationFiled: February 8, 2013Publication date: November 14, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroki NOGUCHI, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Kazutaka Ikegami
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Patent number: 8578318Abstract: In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.Type: GrantFiled: July 30, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Shinichi Yasuda, Shinobu Fujita, Keiko Abe, Tetsufumi Tanamoto, Kazutaka Ikegami, Masato Oda
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Publication number: 20130268795Abstract: According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.Type: ApplicationFiled: December 28, 2012Publication date: October 10, 2013Inventors: Kumiko NOMURA, Shinobu FUJITA, Keiko ABE, Kazutaka IKEGAMI, Hiroki NOGUCHI
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Publication number: 20130246818Abstract: According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.Type: ApplicationFiled: February 21, 2013Publication date: September 19, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kumiko NOMURA, Shinobu FUJITA, Keiko ABE, Kazutaka IKEGAMI, Hiroki NOGUCHI
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Patent number: 8531866Abstract: A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory.Type: GrantFiled: August 19, 2011Date of Patent: September 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazutaka Ikegami, Atsuhiro Kinoshita, Daisuke Hagishima
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Patent number: 8525251Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the firsType: GrantFiled: August 30, 2011Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Hagishima, Atsuhiro Kinoshita, Kazuya Matsuzawa, Kazutaka Ikegami, Yoshifumi Nishi
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Publication number: 20130055189Abstract: In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.Type: ApplicationFiled: July 30, 2012Publication date: February 28, 2013Inventors: Kumiko Nomura, Shinichi Yasuda, Shinobu Fujita, Keiko Abe, Tetsufumi Tanamoto, Kazutaka Ikegami, Masato Oda
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Patent number: 8294489Abstract: A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.Type: GrantFiled: March 16, 2009Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tetsufumi Tanamoto, Hideyuki Sugiyama, Kazutaka Ikegami, Yoshiaki Saito
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Publication number: 20120221616Abstract: According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.Type: ApplicationFiled: March 23, 2012Publication date: August 30, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinichi YASUDA, Kazutaka IKEGAMI
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Publication number: 20120089656Abstract: A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.Type: ApplicationFiled: November 22, 2011Publication date: April 12, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Tetsufumi TANAMOTO, Mari MATSUMOTO, Shinobu FUJITA, Kazutaka IKEGAMI
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Publication number: 20120080739Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the firsType: ApplicationFiled: August 30, 2011Publication date: April 5, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke HAGISHIMA, Atsuhiro KINOSHITA, Kazuya MATSUZAWA, Kazutaka IKEGAMI, Yoshifumi NISHI
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Publication number: 20120026779Abstract: A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory.Type: ApplicationFiled: August 19, 2011Publication date: February 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutaka Ikegami, Atsuhiro Kinoshita, Daisuke Hagishima
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Publication number: 20100073025Abstract: A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.Type: ApplicationFiled: March 16, 2009Publication date: March 25, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Tetsufumi TANAMOTO, Hideyuki SUGIYAMA, Kazutaka IKEGAMI, Yoshiaki SAITO