Patents by Inventor Kazutaka Inoue

Kazutaka Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230054259
    Abstract: A semiconductor device includes a substrate, a semiconductor stacking portion formed on the substrate, a silicon nitride passivation film covering the surface of the semiconductor stacking portion, and oxygen atoms existing at an interface between the silicon nitride passivation film and the semiconductor stacking portion. The semiconductor stacking portion includes a plurality of nitride semiconductor layers. The interfacial oxygen content at the passivation film and stacking portion interface is 0.6×1015 oxygen atoms/cm2 or less.
    Type: Application
    Filed: October 4, 2022
    Publication date: February 23, 2023
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhide SUMIYOSHI, Masaya OKADA, Kazutaka INOUE, Takumi YONEMURA
  • Publication number: 20210066065
    Abstract: A method of forming a silicon nitride passivation film on a nitride semiconductor layer is comprising steps of, introducing a substrate including the nitride semiconductor layer into a reaction furnace, replacing an atmosphere in the reaction furnace from air to an ammonia (NH3) atmosphere or to a hydrogen (H2) atmosphere, raising a temperature in the reaction furnace to a first temperature, maintaining both the temperature in the reaction furnace at the first temperature and the atmosphere in the reaction furnace at the NH3 atmosphere or the H2 atmosphere for three minutes or more, lowering the temperature in the reaction furnace to a second temperature lower than the first temperature, and forming the silicon nitride passivation film by supplying dichlorosilane (SiH2Cl2) into the reaction furnace under the first pressure of 100 Pa or less in the reaction furnace.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 4, 2021
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhide SUMIYOSHI, Masaya OKADA, Kazutaka INOUE, Takumi YONEMURA
  • Publication number: 20190074370
    Abstract: A semiconductor device made of primarily nitride semiconductor materials is disclosed. The semiconductor device includes a substrate; a semiconductor stack on the substrate; electrodes of a gate, a source, and a drain each provided on the semiconductor stack, where the gate electrode contains nickel (Ni); a Si compound covering surfaces of the semiconductor stack; an aluminum oxide (Al2O3) film covering the gate electrode exposed from the Si compound; and another Si compound covering the Al2O3 film and the Si compound exposed from the Al2O3 film. A feature of the semiconductor device of the invention is that the Al2O3 film exposes the Si compound at least between the gate electrode and the drain electrode.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kenta SUGAWARA, Kazutaka INOUE
  • Patent number: 10123719
    Abstract: A technique to detect an eye potential of a wearer of an eyewear by using an electrode abutting on the glabella of the wearer has been known, but it is desirable to surely cause the electrode to abut on the glabella so as to prevent deterioration in the detection accuracy of detecting a biosignal indicating an eye potential, myogenic potential, brain wave or the like. In view of this, an eyewear including: a frame; a first electrode that abuts on a glabella of a wearer of the eyewear; and an electrode holding unit that holds the first electrode such that a distance between the frame and the first electrode is changeable is included.
    Type: Grant
    Filed: February 4, 2018
    Date of Patent: November 13, 2018
    Assignee: JINS Inc.
    Inventors: Kazutaka Inoue, Susumu Ichinohe, Jyunko Nakajima
  • Publication number: 20180160973
    Abstract: A technique to detect an eye potential of a wearer of an eyewear by using an electrode abutting on the glabella of the wearer has been known, but it is desirable to surely cause the electrode to abut on the glabella so as to prevent deterioration in the detection accuracy of detecting a biosignal indicating an eye potential, myogenic potential, brain wave or the like. In view of this, an eyewear including: a frame; a first electrode that abuts on a glabella of a wearer of the eyewear; and an electrode holding unit that holds the first electrode such that a distance between the frame and the first electrode is changeable is included.
    Type: Application
    Filed: February 4, 2018
    Publication date: June 14, 2018
    Inventors: Kazutaka INOUE, Susumu ICHINOHE, Jyunko NAKAJIMA
  • Patent number: 9883816
    Abstract: A technique to detect an eye potential of a wearer of an eyewear by using an electrode abutting on the glabella of the wearer has been known, but it is desirable to surely cause the electrode to abut on the glabella so as to prevent deterioration in the detection accuracy of detecting a biosignal indicating an eye potential, myogenic potential, brain wave or the like. In view of this, an eyewear including: a frame; a first electrode that abuts on a glabella of a wearer of the eyewear; and an electrode holding unit that holds the first electrode such that a distance between the frame and the first electrode is changeable is included.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: February 6, 2018
    Assignee: JIN CO., LTD.
    Inventors: Kazutaka Inoue, Susumu Ichinohe, Jyunko Nakajima
  • Publication number: 20170027470
    Abstract: A technique to detect an eye potential of a wearer of an eyewear by using an electrode abutting on the glabella of the wearer has been known, but it is desirable to surely cause the electrode to abut on the glabella so as to prevent deterioration in the detection accuracy of detecting a biosignal indicating an eye potential, myogenic potential, brain wave or the like. In view of this, an eyewear including: a frame; a first electrode that abuts on a glabella of a wearer of the eyewear; and an electrode holding unit that holds the first electrode such that a distance between the frame and the first electrode is changeable is included.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Inventors: Kazutaka INOUE, Susumu ICHINOHE, Jyunko NAKAJIMA
  • Patent number: 9012958
    Abstract: A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with an underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1?7, where L is the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; and d1 is the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kazutaka Inoue
  • Patent number: 8969920
    Abstract: A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Masaki Ueno, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
  • Patent number: 8941174
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: January 27, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Patent number: 8896058
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 25, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Patent number: 8890239
    Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Mitsunori Yokoyama, Kazutaka Inoue, Masaya Okada, Yu Saitoh
  • Publication number: 20140312357
    Abstract: A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with a underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1>=7, where L=the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; d1 the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 23, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Kazutaka INOUE
  • Patent number: 8816398
    Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
  • Patent number: 8592919
    Abstract: A semiconductor device includes source electrodes having source fingers, drain electrodes having drain fingers, and gate electrodes having bent portions between steps formed in stepwise side portions of source fingers and steps formed in stepwise side portions of drain fingers and being bent in the bent portions along the source fingers and the drain fingers. A shape of the stepwise side portion of one source finger and that of the stepwise portion of the corresponding drain finger are symmetrical about a midpoint of an imaginary line that connects the other end of the source finger and the other end of the corresponding drain finger.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kazutaka Inoue
  • Publication number: 20130248876
    Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.
    Type: Application
    Filed: July 26, 2011
    Publication date: September 26, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Mitsunori Yokoyama, Kazutaka Inoue, Masaya Okada, Yu Saitoh
  • Publication number: 20130240900
    Abstract: There is provided a semiconductor device or the like which includes a channel and a gate electrode in an opening and in which electric field concentration near a bottom portion of the opening can be reduced. The semiconductor device includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer. An opening 28 extends from the top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located in the opening, the regrown layer 27 including an electron supply layer 26 and an electron drift layer 22, a source electrode S, a drain electrode D, a gate electrode G located on the regrown layer, and a semiconductor impurity adjustment region 31 disposed in the bottom portion of the opening. The impurity adjustment region 31 is a region that promotes a potential drop from the drain electrode side to the gate electrode side in a potential distribution in an off-state.
    Type: Application
    Filed: October 17, 2011
    Publication date: September 19, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Kazutaka Inoue, Mitsunori Yokoyama, Yu Saitoh, Masaya Okada
  • Publication number: 20130234156
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.
    Type: Application
    Filed: October 17, 2011
    Publication date: September 12, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Publication number: 20130221434
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.
    Type: Application
    Filed: October 5, 2011
    Publication date: August 29, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Publication number: 20130181255
    Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.
    Type: Application
    Filed: July 6, 2011
    Publication date: July 18, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama