Abstract: A thermal barrier coating material can prevent spall-off from occurring during operation at high temperatures and has a high heat insulating effect. A turbine parts and a gas turbine that are protected with the thermal barrier coating material are also provided. The thermal barrier coating material of the present invention comprises a ceramic layer 23, which is formed on a high temperature heat-resistant alloy base 21 to protect the base 21 from high temperatures, the ceramic layer 23 being applied via a bonding coat layer 22 provided as a metal bonding layer and is made of ZrO2 with Er2O3 added thereto as a stabilizing agent. The turbine parts and the gas turbine of the present invention are coated with the thermal barrier coating material on the surfaces thereof.

Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.

Abstract: Well printing a specified pattern even when exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm.

Abstract: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises properly using a photomask having light blocking patterns made of a metal and another photomask having light blocking patterns made of a resist film upon exposure treatment, depending on the fabrication step of the semiconductor integrated circuit device.

Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested.

Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Abstract: A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states.

Abstract: An interconnector material for use in electrochemical cells having Y.sub.2 O.sub.3 -stabilized ZrO.sub.2 as a solid electrolyte, said interconnector material comprising a lanthanum chromite material of the following general formula:(La.sub.1-x Sr.sub.x)(Cr.sub.1-y M.sub.y)O.sub.3,where M is Zr or Ti, x is in the range of 0.1 to 0.2, and y is in the range of 0.05 to 0.2.

Abstract: An extra large number-of-input complex logic circuit, employed inside a microprocessor for performing a large number of controls and arithmetic operations, is constructed utilizing N(N.gtoreq.2) number of a unit logic circuit each comprising M(M.gtoreq.1) input CMOS logic circuits and one bipolar transistor, whereby respective outputs are integrated to produce one output in response to M.times.N number input signals to provide a high speed, high density integration and low power consumption microprocessor.

Abstract: In a parallel computer system in which many microprocessor elements are disposed at least in a two dimensional array to communicate data therebetween at a high speed, n bidirectional buses XBi and m bidirectional YBi are respectively arranged in X and Y directions to dispose m by n data processor elements CPUij at intersections of the buses XBi and YBj, thereby connecting these elements respectively to the associated buses XBi and YBj. Each processor element has a unit for selectively establishing a connection between the bus XBi and the bus YBj which are coupled thereto. In a data transfer between two elements sharing neither one of the bidirectional buses in the X and Y directions, there is selected an element which is connected to one of the X-directional-buses linked to one of the elements and which is connected to, one of the Y-directional buses linked to the other one thereof to use the selected element as a relay for establishing a conductive route between the buses.

Abstract: A composite circuit device of bipolar transistors and MOS transistors has a series connection of an NPN transistor for pull-up and a PNP transistor for pull-down. The composite circuit device has independent base drive circuits so provided that the base of the NPN transistor for pull-up is electrically isolated from the base of the PNP transistor for pull-down during the on-off switching operation. The composite circuit device is also provided with base precharge circuitry for pre-charging the base of the PNP transistor during the off operation state thereof. A composite circuit is also provided with circuitry for enhancing the turn-on switching speed of the pull-down PNP transistor. Additionally, a composite circuit of bipolar transistors and MOS transistors is constituted by a switch having a high input impedance and low on-resistance which can be applied as a component of an electronic circuit.

Abstract: A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states.

Abstract: In order to reduce undesirable output noise, an output circuit is provided which includes a first output MOSFET which is interposed between an output terminal and a first power source voltage, and a second output MOSFET which is interposed between the output terminal and a second power source voltage. In particular, in accordance with one aspect of the invention, a feedback circuit is interposed between the output terminal and the gate of the first output MOSFET or/and between the output terminal and the gate of the second output MOSFET to negatively feedback voltage to provide a gentle level change for the output voltage. In other embodiments, a short-circuit arrangement is provided which is interposed between the gate and source of the first output MOSFET or/and between the gate and source of the second output MOSFET.