Abstract: Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.

Abstract: A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes an opening through an interpoly dielectric layer, floating gate layer, and tunnel dielectric layer, the opening separated from the substrate surface by a select gate dielectric on the substrate surface, the opening filled by a control gate layer.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: Non-volatile storage devices and methods for fabricating non-volatile storage device are described. Sidewalls of the memory cells and their associated word line may be covered with silicon oxide. Silicon nitride covers the silicon oxide adjacent to the word lines, which may provide protection for the word lines during fabrication. However, silicon nitride can trap charges, which can degrade operation if the trapped charges are near a charge trapping region of a memory cell. Thus, the silicon nitride does not cover the silicon oxide adjacent to charge storage regions of the memory cells, which can improve device operation. For example, memory cell current may be increased. Techniques for forming such a device are also disclosed. One aspect includes a method that uses a sacrificial material to control formation of a silicon nitride layer when forming a memory device.

Abstract: A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer.

Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.

Abstract: A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first metal ring surrounding the semiconductor element; an insulation film formed to cover the semiconductor element and having the first metal ring disposed therein; and a groove formed in the insulation film; wherein: the first metal ring is formed by laminating multiple metal layers in such a manner that respective outside lateral faces of the multiple metal layers are flush with each other, or that outside lateral face of each of the multiple metal layers which is positioned above an underlying metal layer is positioned more inside than outside lateral face of the underlying metal layer; and the groove has first bottom which is disposed inside the first metal ring and extending to a depth of upper surface of an uppermost metal layer of the first metal ring.

Abstract: A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher.

Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.

Abstract: A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area.

Abstract: An electronic camera includes an imaging device. The imaging device carries out an exposing operation for exposing an object scene and an amplifying operation for amplifying a raw image signal generated by the exposing operation, according to a set imaging parameter. A CPU selects one program chart satisfying a parameter condition, from a plurality of program charts stored in a flash memory, and extracts three imaging parameters from the selected program chart. The extracted imaging parameters are set to the imaging device. The imaging parameter here includes exposure time, amount of aperture, and AGC gain as parameter elements. In addition, the parameter condition includes an AGC gain condition in that each of three AGC gains defining respectively the three imaging parameters is equal to or less than a predetermined value and an exposure time condition in that three exposure times defining respectively the three imaging parameters are shorter.

Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface of the plurality of silicon substrates in a batch process after annealing the silicon substrates.

Abstract: An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact compensation, and high-temperature annealing is carried out in order to activate implanted impurities. Subsequently, an interlayer insulation film, a storage capacitor, and another interlayer insulation film are formed in sequence. Then, contact holes reaching a part of wiring layers are formed in the peripheral circuit part while, in the guard ring part, a trench reaching a diffusion layer is formed. Next, a barrier metal film is formed in each of the contact holes and the trench, and further, a contact plug comprising, for example, a W film is buried therein.

Abstract: A first insulating film consisting of an insulating material is formed on a major surface of a semiconductor substrate. On the first insulating film, a wire comprising a first conductive layer, which contains one of elemental Ti and a Ti compound, is formed. Cover films consisting of silicon nitride cover the upper surface, the bottom surface, and the side surfaces of the wire having a multilayer structure. Accordingly, a semiconductor device in which insulation defects are unlikely to occur even when the degree of integration is increased can be provided.