Patents by Inventor Kazuto Nishida
Kazuto Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6926796Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is corrected, the bumps are compressed, and the insulating resin is hardened.Type: GrantFiled: January 26, 2000Date of Patent: August 9, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
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Publication number: 20050168961Abstract: A stereoscopically connected structure is made up of a first circuit board and a second circuit board which are mounted with other electronic components, and a relay board having a recess which is mounted with an electronic component and is provided with a lead-out wiring extending from the electronic component, and also having a land part to be connected with the lead-out wiring on one of the surfaces of the relay board that face the first circuit board and second circuit board. Thus the relay board can mount the electronic component thereon as well as connect the first circuit board and the second circuit board, thereby achieving high density mounting.Type: ApplicationFiled: November 10, 2004Publication date: August 4, 2005Inventors: Masahiro Ono, Shigeru Kondo, Kazuhiro Nishikawa, Yoshihiko Yagi, Kazuto Nishida
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Publication number: 20050155706Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.Type: ApplicationFiled: February 23, 2005Publication date: July 21, 2005Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
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Publication number: 20050093172Abstract: An electronic circuit device has a substrate having a wiring pattern, an electronic component electrically connected to a terminal section of the wiring pattern by contacting a projection electrode with it, a cover that is disposed at a position facing the substrate and grapples the electronic component between it and the substrate, and a resin layer made of thermoplastic resin filled in a gap between the substrate and the cover. The gap includes a space in a connection region except an electric connection part between the projection electrode and the terminal section. The electronic component is adhered to the substrate and the substrate is adhered to the cover through the resin layer. Thus, the electronic circuit device having high connection reliability and high mass productivity, and a method and apparatus for manufacturing the electronic circuit device can be provided.Type: ApplicationFiled: October 7, 2004Publication date: May 5, 2005Inventors: Norihito Tsukahara, Kazuhiro Nishikawa, Kazuto Nishida
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Publication number: 20040155336Abstract: It is possible to prevent deterioration of a soldering portion and improve strength of thermal fatigue resistance by providing barrier metal layers on at least one of lead and land to cover parent materials comprising Cu-containing materials, feeding a soldering material between the lead and the land and allowing to contact in a fused condition with barrier metal layers and solidify, and thus soldering together the lead and the land.Type: ApplicationFiled: February 3, 2004Publication date: August 12, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Atsushi Yamaguchi, Kazuto Nishida, Masato Hirano
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Publication number: 20030166313Abstract: A semiconductor element mounting method is provided with high productivity. The method includes forming bumps on electrodes of a wafer in which a plurality of semiconductor elements have been formed, temporarily compression-bonding the wafer and an interposer via an insulative resin, curing the resin by heating and pressurization so that the wafer and the interposer are finally compression-bonded, where the electrodes of the wafer and electrodes of the interposer are bonded to each other, respectively, and where insulative resin overflowing from between the wafer and the interposer flows into grooves disposed so as to be coincident with dicing lines of the wafer, thus giving a uniform flow of the insulative resin, and thereafter, cutting and separating into individual semiconductor elements.Type: ApplicationFiled: September 25, 2002Publication date: September 4, 2003Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Hiroyuki Otani
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Publication number: 20030138993Abstract: A method for manufacturing a semiconductor device whereby semiconductor elements like semiconductor bare chips are mounted with high productivity on both surfaces of a circuit board while preventing the board from warping, and an apparatus for manufacturing a semiconductor device for faithfully embodying the manufacturing method. Semiconductor elements temporarily fixed on both surfaces of a circuit board are heated while being pressurized in directions to be each pressed against the board, whereby adhesive on both surfaces of the board is thermally set simultaneously and bumps on each semiconductor elements are press-bonded to their opposing board electrodes on the board to be electrically connected. Ultraviolet rays are irradiated to a circumference of mixed curing adhesive applied to at least one surface of the circuit board to form an ultraviolet curing part only on the circumference of the adhesive, thereby increasing strength for temporarily fixing the semiconductor elements to the circuit board.Type: ApplicationFiled: December 26, 2002Publication date: July 24, 2003Applicant: Matsushita Elec Ind. Co., Ltd.Inventors: Koujiro Nakamura, Yoshihiko Yagi, Michiro Yoshino, Kazuto Nishida
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Publication number: 20030092326Abstract: An electronic component 1-1 and a circuit formation article 6-1 are bonded together with a bonding material 5 containing resin interposed therebetween. In a state that bumps 2 of an electronic-component bonding region 6a-1 and electrodes 7 of the circuit formation article are in mutual electrical contact, the electronic component and the circuit formation article are thermocompression-bonded to each other by a bonding-material flow regulating member 303 of the electronic-component bonding region under regulation of flow of the bonding material toward a peripheral portion, of the electronic-component bonding region, so that the bonding material is cured.Type: ApplicationFiled: December 16, 2002Publication date: May 15, 2003Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Shuji Ono, Hiroyuki Otani
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Publication number: 20030049937Abstract: The present invention provides an apparatus and a method for surface treatment to substrates whereby the quality of substrates can be maintained by preventing an excessive plasma treatment to substrates. In carrying out the plasma treatment to a surface of the substrate in a reaction chamber, there are provided an emission spectroscopic analysis device or a mass analyzer, and a controller, so that an energy of ions in plasma is controlled to decrease when, e.g., bromine included in the substrate is detected, and the surface treatment to the substrate is controlled to stop when removing impurities of the substrate is detected to end. The bromine once separated from the substrate is prevented from adhering again to the substrate to corrode the substrate. Moreover, ions are prevented from being excessively irradiated to the substrate when the removal of impurities ends, thereby reducing damages to the substrate. The substrate quality is maintained accordingly.Type: ApplicationFiled: September 4, 2002Publication date: March 13, 2003Inventors: Naoki Suzuki, Kazuto Nishida, Kazuyuki Tomita
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Patent number: 6156150Abstract: A method and apparatus for separating an IC component (1) from a board (3). The method includes the processes of positioning a tool (21) just above the IC component, thereafter moving the tool down into a specified position, making the tool cover the IC component that is mounted on the board via an adhesive material, solder, or paste, and separating the IC component from the board by turning the tool. Through these processes, the IC component can be separated with a relatively small force, so that cracking of the IC component and damage to the board can be suppressed to a minimum.Type: GrantFiled: October 14, 1998Date of Patent: December 5, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazuto Nishida
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Patent number: 6086441Abstract: A method is disclosed for connecting electrodes of a plasma display panel. The method includes overlapping a thick film electrode formed on a glass substrate with an electrode of a flexible substrate via an adhesive sheet having conductive particles dispersed therein, then, heating and pressuring from above the flexible substrate with a pressuring tool, to thereby set the adhesive sheet, and finally electrically connecting the electrode of the glass substrate and the electrode of the flexible substrate with each other.Type: GrantFiled: April 29, 1998Date of Patent: July 11, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Akiguchi, Kazuto Nishida
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Patent number: 5917156Abstract: Copper electrodes are formed on a circuit board to be bonded with leads of a TAB driving liquid crystal. A pre-deposit solder receiver having solder printed thereon is also provided on the circuit board in alignment with and prior to an electrode to be first bonded with a lead, to form a sufficient solder pool between plural electrodes and a bottom wall of a soldering iron. Solder/bonding is accordingly realized efficiently even from a starting electrode E1. Also, an excessive solder receiver may be provided in alignment with and after an electrode to be last bonded with a lead.Type: GrantFiled: August 29, 1995Date of Patent: June 29, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuhiro Nobori, Kazuto Nishida, Norihito Tsukahara
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Patent number: 5858806Abstract: A method wherein an IC component is mounted to electrodes provided in a transparent portion of a flat panel display with interposition of an anisotropic conductive adhesive or film, includes steps of detecting, when mounting the IC component onto the transparent portion of the flat panel display for temporary bonding to the adhesive or film, positional displacement amounts of first positional alignment portions in two positions of the mounted IC component relative to second positional alignment portions in two positions of the transparent portion of the flat panel display in correspondence with the first positional alignment portions by a camera from a side of the flat panel display opposite from a side on which the IC component is mounted, thereby inspecting positional alignment state of bumps of the IC component with the electrodes of the flat panel display, feeding back the positional displacement amount of the IC component with respect to the flat panel display when the positional alignment state is not aType: GrantFiled: March 22, 1996Date of Patent: January 12, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazuto Nishida
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Patent number: 5462626Abstract: A bonding method of for external leads which includes the steps of registering the external leads of an IC component with electrodes of a circuit substrate, setting an external lead retaining surface of a bonding tool on a flat outer tab obtained by coating plural outer end parts of the external leads of the registered IC component with resin, and bringing the external leads in touch with the corresponding electrodes. A laster beam irradiates one of the external leads registered on one of the electrodes to thereby bond them, and cooling gas is jetted on a bonding part of the external lead to cool a bonding part of the external lead and the electrode. During the irradiating step, the one of the external leads registered on one of the corresponding electrodes can be pressed against the electrode to bond the bonding part of the electrode and the external lead.Type: GrantFiled: July 29, 1993Date of Patent: October 31, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinji Kanayama, Akira Kabeshita, Kenichi Nishino, Satoshi Ohnakada, Takahiko Murata, Kazuhiro Kimura, Kazuto Nishida
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Patent number: 5240170Abstract: A method for bonding leads of an IC component with electrodes of a circuit board includes the steps of using a mounting device to hold the IC component with flat portions of the leads inclined downward, mounting the IC component on the circuit board at a predetermined position thereof with the IC component held by the mounting device, moving the mounting device toward the circuit board to compress the IC component against the circuit board at the predetermined position while allowing the leads to flex to accommodate for nonuniformity in the heights of metal pieces to be bonded with the electrodes and bending of the circuit board. In this manner, the flat portions of the leads are brought into close contact with the electrodes. The leads are then irradiated with an optical beam so as to melt the metal pieces of the electrodes for bonding of the leads to the circuit board.Type: GrantFiled: June 5, 1992Date of Patent: August 31, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuto Nishida, Kazuhiro Nobori, Yoshifumi Kitayama, Keiji Saeki