Patents by Inventor Kazutoyo Takano
Kazutoyo Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230028753Abstract: A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki NAKAMURA, Kazutoyo TAKANO
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Patent number: 11531053Abstract: Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.Type: GrantFiled: November 10, 2020Date of Patent: December 20, 2022Assignee: Mitsubishi Electric CorporationInventors: Kazutoyo Takano, Hiroyuki Nakamura
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Patent number: 11527449Abstract: A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.Type: GrantFiled: December 1, 2020Date of Patent: December 13, 2022Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Nakamura, Kazutoyo Takano
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Patent number: 11251177Abstract: A semiconductor device 1 has an IGBT region and a MOSFET region. A plurality of channel doped P layers formed in the MOSFET region include a trench-adjacent channel doped P layer whose side surface is in contact with a boundary trench gate formed between the IGBT region and the MOSFET region. A formation depth of the trench-adjacent channel doped P layer is set deeper than a formation depth of the boundary trench gate. In the MOSFET region, an N type MOSFET having a planar structure is configured including a channel region in the channel doped P layer, a gate insulating film in an interlayer oxide film, and a gate polysilicon serving as a planar gate.Type: GrantFiled: February 14, 2020Date of Patent: February 15, 2022Assignee: Mitsubishi Electric CorporationInventors: Kazutoyo Takano, Hiroyuki Nakamura
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Publication number: 20210384088Abstract: A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.Type: ApplicationFiled: December 1, 2020Publication date: December 9, 2021Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki NAKAMURA, Kazutoyo TAKANO
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Publication number: 20210223305Abstract: Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.Type: ApplicationFiled: November 10, 2020Publication date: July 22, 2021Applicant: Mitsubishi Electric CorporationInventors: Kazutoyo TAKANO, Hiroyuki NAKAMURA
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Publication number: 20200388608Abstract: A semiconductor device 1 has an IGBT region and a MOSFET region. A plurality of channel doped P layers formed in the MOSFET region include a trench-adjacent channel doped P layer whose side surface is in contact with a boundary trench gate formed between the IGBT region and the MOSFET region. A formation depth of the trench-adjacent channel doped P layer is set deeper than a formation depth of the boundary trench gate. In the MOSFET region, an N type MOSFET having a planar structure is configured including a channel region in the channel doped P layer, a gate insulating film in an interlayer oxide film, and a gate polysilicon serving as a planar gate.Type: ApplicationFiled: February 14, 2020Publication date: December 10, 2020Applicant: Mitsubishi Electric CorporationInventors: Kazutoyo TAKANO, Hiroyuki NAKAMURA
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Patent number: 10665670Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.Type: GrantFiled: July 20, 2016Date of Patent: May 26, 2020Assignee: Mitsubishi Electric CorporationInventors: Kazutoyo Takano, Kazushige Matsuo, Masayoshi Hirao, Junji Yahiro
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Publication number: 20190157389Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.Type: ApplicationFiled: July 20, 2016Publication date: May 23, 2019Applicant: Mitsubishi Electric CorporationInventors: Kazutoyo TAKANO, Kazushige MATSUO, Masayoshi HIRAO, Junji YAHIRO
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Publication number: 20170062412Abstract: A transistor element includes: a first semiconductor substrate on which a first transistor cell region is formed; a first gate electrode pad formed on the first semiconductor substrate and connected to a gate in the first transistor cell region; a relay electrode pad formed on the first semiconductor substrate; and a gate resistance formed on the first semiconductor substrate and connected between the first gate electrode pad and the relay electrode pad.Type: ApplicationFiled: April 19, 2016Publication date: March 2, 2017Applicant: Mitsubishi Electric CorporationInventors: Makoto KAWANO, Kazutoyo TAKANO, Yukitaka HORI
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Patent number: 9406571Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor wafer including a plurality of semiconductor devices sandwiching a dicing region and an inline inspection monitor arranged in the dicing region; after forming the semiconductor wafer, conducting an inline inspection of the semiconductor device by using the inline inspection monitor; and after the inline inspection, dicing the semiconductor wafer along the dicing region to separate the semiconductor devices individually. The step of forming the semiconductor wafer includes: simultaneously forming a first diffusion layer of the semiconductor device and a second diffusion layer of the inline inspection monitor; forming a metal layer on the first and second diffusion layer; and at least partly removing the metal layer on the second diffusion layer. When the semiconductor wafer is diced, a portion from which the metal layer has been removed is cut by a dicing blade on the second diffusion layer.Type: GrantFiled: September 15, 2014Date of Patent: August 2, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuya Yoshida, Kazutoyo Takano
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Publication number: 20150221564Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor wafer including a plurality of semiconductor devices sandwiching a dicing region and an inline inspection monitor arranged in the dicing region; after forming the semiconductor wafer, conducting an inline inspection of the semiconductor device by using the inline inspection monitor; and after the inline inspection, dicing the semiconductor wafer along the dicing region to separate the semiconductor devices individually. The step of forming the semiconductor wafer includes: simultaneously forming a first diffusion layer of the semiconductor device and a second diffusion layer of the inline inspection monitor; forming a metal layer on the first and second diffusion layer; and at least partly removing the metal layer on the second diffusion layer. When the semiconductor wafer is diced, a portion from which the metal layer has been removed is cut by a dicing blade on the second diffusion layer.Type: ApplicationFiled: September 15, 2014Publication date: August 6, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuya YOSHIDA, Kazutoyo TAKANO
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Patent number: 9093310Abstract: A semiconductor device including a semiconductor layer of a first conductivity type in a cell region, a first base layer of a second conductivity type on the semiconductor layer in the cell region; a second base layer of the second conductivity type on the semiconductor layer in an intermediate region; a conductive region of a first conductivity type in the first base layer; a gate electrode on a channel region placed between the conductive region and the semiconductor layer; a first electrode connected to the first and second base layers; a second electrode connected to the semiconductor layer; and a gate pad on the semiconductor layer via an insulating film in a pad region and connected to the gate electrode, an impurity concentration gradation in the gate pad side of the second base layer has a gentler VLD structure than an impurity concentration gradation in the first base layer.Type: GrantFiled: September 14, 2012Date of Patent: July 28, 2015Assignee: Mitsubishi Electric CorporationInventor: Kazutoyo Takano
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Publication number: 20130187240Abstract: A semiconductor device including a semiconductor layer of a first conductivity type in a cell region, a first base layer of a second conductivity type on the semiconductor layer in the cell region; a second base layer of the second conductivity type on the semiconductor layer in an intermediate region; a conductive region of a first conductivity type in the first base layer; a gate electrode on a channel region placed between the conductive region and the semiconductor layer; a first electrode connected to the first and second base layers; a second electrode connected to the semiconductor layer; and a gate pad on the semiconductor layer via an insulating film in a pad region and connected to the gate electrode, an impurity concentration gradation in the gate pad side of the second base layer has a gentler VLD structure than an impurity concentration gradation in the first base layer.Type: ApplicationFiled: September 14, 2012Publication date: July 25, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kazutoyo TAKANO
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Patent number: 8377832Abstract: A method for manufacturing a semiconductor device includes the steps of forming a P-type region on a surface of a semiconductor substrate, forming at least one Al electrode on the P-type region, forming an interlayer film in contact with the at least one Al electrode, the interlayer film being of a material which is less reactive with Si than is Al, and forming a semi-insulating film on the interlayer film, the semi-insulating film containing Si.Type: GrantFiled: March 2, 2009Date of Patent: February 19, 2013Assignee: Mitsubishi Electric CorporationInventors: Kazutoyo Takano, Junichi Murakami, Tadaharu Minato
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Patent number: 8278706Abstract: A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness.Type: GrantFiled: June 24, 2010Date of Patent: October 2, 2012Assignee: Mitsubishi Electric CorporationInventor: Kazutoyo Takano
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Patent number: 7955930Abstract: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.Type: GrantFiled: March 10, 2010Date of Patent: June 7, 2011Assignee: Mitsubishi Electric CorporationInventors: Tadaharu Minato, Kazutoyo Takano
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Publication number: 20110062514Abstract: A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness.Type: ApplicationFiled: June 24, 2010Publication date: March 17, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kazutoyo Takano
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Publication number: 20100167516Abstract: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.Type: ApplicationFiled: March 10, 2010Publication date: July 1, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tadaharu Minato, Kazutoyo Takano
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Patent number: 7701003Abstract: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.Type: GrantFiled: December 14, 2007Date of Patent: April 20, 2010Assignee: Mitsubishi Electric CorporationInventors: Tadaharu Minato, Kazutoyo Takano