Patents by Inventor Kazuya Endo

Kazuya Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10768741
    Abstract: A semiconductor device configured to drive a display panel in a display period, and perform touch sensing on the display panel in a touch sensing period after the display period. In a last horizontal sync period of the display period, the semiconductor device drives a first source line with a drive voltage of a first polarity, and a second source line with a drive voltage of a second polarity different from the first polarity. is the semiconductor is configured to output a first dummy pulse having first polarity and a voltage level based on the second display data to the first source line in a transition period between the display period and the touch sensing period.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 8, 2020
    Assignee: Creative Legend Semiconductor (Hong Kong) Limited
    Inventors: Kazuya Endo, Shinobu Nohtomi, Atsushi Shikata, Kentaro Suzuki
  • Patent number: 10599254
    Abstract: In a semiconductor device in which a reference voltage is generated by a reference voltage generation circuit, and the same reference voltage generated is used in a plurality of circuit units for the purpose of generating a voltage, a sampling and holding circuit of the reference voltage is provided in order to provide a standard voltage to the circuit units. A sampling and holding control circuit that controls the sampling and holding circuit instructs the sampling and holding circuit to perform a sampling operation of the reference voltage in case that the semiconductor device operates in a state where power supply noise of the reference voltage generation circuit falls within a predetermined range, and instructs the sampling and holding circuit to perform a holding operation of the reference voltage in case that the semiconductor device operates in a state where the power supply noise exceeds the predetermined range.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 24, 2020
    Assignee: Synaptics Japan GK
    Inventor: Kazuya Endo
  • Patent number: 10372248
    Abstract: The semiconductor device is intended for connection with an in-cell type display touch panel having a plurality of common electrodes, a reference voltage for display is applied to the common electrodes in a display drive period, and the common electrodes serve as sensor electrodes in a touch detection period. The semiconductor device includes a DC level shift circuit operable to shift the DC level of a toggle signal output by a toggle drive circuit to the reference voltage. The semiconductor device supplies the reference voltage to the common electrodes of the display touch panel in the display drive period, and performs a guarding action in which at least a part of the plurality of common electrodes is supplied with a toggle signal shifted in DC level in the touch detection period.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 6, 2019
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Kazuya Endo, Shinobu Nohtomi, Nobukazu Tanaka, Tomohiro Hirakawa, Hiroshi Takeyama, Takayuki Noto, Petr Shepelev
  • Publication number: 20180335888
    Abstract: A semiconductor device configured to drive a display panel in a display period, and perform touch sensing on the display panel in a touch sensing period after the display period. In a last horizontal sync period of the display period, the semiconductor device drives a first source line with a drive voltage of a first polarity, and a second source line with a drive voltage of a second polarity different from the first polarity. is the semiconductor is configured to output a first dummy pulse having first polarity and a voltage level based on the second display data to the first source line in a transition period between the display period and the touch sensing period.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Inventors: Kazuya ENDO, Shinobu NOHTOMI, Atsushi SHIKATA, Kentaro SUZUKI
  • Publication number: 20180107309
    Abstract: The semiconductor device is intended for connection with an in-cell type display touch panel having a plurality of common electrodes, a reference voltage for display is applied to the common electrodes in a display drive period, and the common electrodes serve as sensor electrodes in a touch detection period. The semiconductor device includes a DC level shift circuit operable to shift the DC level of a toggle signal output by a toggle drive circuit to the reference voltage. The semiconductor device supplies the reference voltage to the common electrodes of the display touch panel in the display drive period, and performs a guarding action in which at least a part of the plurality of common electrodes is supplied with a toggle signal shifted in DC level in the touch detection period.
    Type: Application
    Filed: October 19, 2016
    Publication date: April 19, 2018
    Inventors: Kazuya ENDO, Shinobu NOHTOMI, Nobukazu TANAKA, Tomohiro HIRAKAWA, Hiroshi TAKEYAMA, Takayuki NOTO, Petr SHEPELEV
  • Publication number: 20180074647
    Abstract: In a semiconductor device in which a reference voltage is generated by a reference voltage generation circuit, and the same reference voltage generated is used in a plurality of circuit units for the purpose of generating a voltage, a sampling and holding circuit of the reference voltage is provided in order to provide a standard voltage to the circuit units. A sampling and holding control circuit that controls the sampling and holding circuit instructs the sampling and holding circuit to perform a sampling operation of the reference voltage in case that the semiconductor device operates in a state where power supply noise of the reference voltage generation circuit falls within a predetermined range, and instructs the sampling and holding circuit to perform a holding operation of the reference voltage in case that the semiconductor device operates in a state where the power supply noise exceeds the predetermined range.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventor: Kazuya ENDO
  • Patent number: 9846504
    Abstract: In a semiconductor device in which a reference voltage is generated by a reference voltage generation circuit, and the same reference voltage generated is used in a plurality of circuit units for the purpose of generating a voltage, a sampling and holding circuit of the reference voltage is provided in order to provide a standard voltage to the circuit units. A sampling and holding control circuit that controls the sampling and holding circuit instructs the sampling and holding circuit to perform a sampling operation of the reference voltage in case that the semiconductor device operates in a state where power supply noise of the reference voltage generation circuit falls within a predetermined range, and instructs the sampling and holding circuit to perform a holding operation of the reference voltage in case that the semiconductor device operates in a state where the power supply noise exceeds the predetermined range.
    Type: Grant
    Filed: September 20, 2014
    Date of Patent: December 19, 2017
    Assignee: Synaptics Japan GK
    Inventor: Kazuya Endo
  • Publication number: 20170179789
    Abstract: There is provided an electric motor suitable for a vacuum cleaner, which achieves high output and high efficiency in operation at a rotation of 30,000 rpm or more, required for a motor for a vacuum cleaner, as well as enables its life to be extended. The electric motor includes a rotor core and a commutator that are coaxially fixed to a rotating shaft, and a stator core arranged around the rotor core. The rotor core and the stator core comprises a plurality of rotor core elements and a plurality of stator core elements, each formed of a thin electromagnetic steel plate having a thickness of less than 0.3 mm, are stacked and fixed in layers. Each of the plurality of rotor core elements has a diameter including a tip of each of teeth, within a range of approximately 35 mm to 40 mm, and each of the teeth has a length in a longitudinal direction that is one-third or more of a radius of the rotor core element.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 22, 2017
    Inventor: Kazuya ENDO
  • Patent number: 9195352
    Abstract: Provided is a touch sensor panel which can increase the detection sensitivity of a touch relatively readily. The touch sensor panel controller supplies drive electrodes of a touch sensor panel with a high-voltage AC drive signal with its low level set to a negative voltage and drives them. The time of change of a drive waveform supplied to the drive electrodes of the touch sensor panel is shifted relative to the time of change of a drive waveform supplied to a display scan electrode. The touch sensor panel controller uses a charge pump in synchronization with clock signals of more than one phase to produce a high drive voltage to activate drive electrodes of the touch sensor panel, and the clock signals of more than one phase are initialized each time the drive electrode is subjected to AC pulse driving.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: November 24, 2015
    Assignee: SYNAPTICS DISPLAY DEVICES GK
    Inventors: Akihito Akai, Tatsuya Ishii, Kazuya Endo, Shinobu Notomi, Akihiro Kodama
  • Publication number: 20150091829
    Abstract: In a semiconductor device in which a reference voltage is generated by a reference voltage generation circuit, and the same reference voltage generated is used in a plurality of circuit units for the purpose of generating a voltage, a sampling and holding circuit of the reference voltage is provided in order to provide a standard voltage to the circuit units. A sampling and holding control circuit that controls the sampling and holding circuit instructs the sampling and holding circuit to perform a sampling operation of the reference voltage in case that the semiconductor device operates in a state where power supply noise of the reference voltage generation circuit falls within a predetermined range, and instructs the sampling and holding circuit to perform a holding operation of the reference voltage in case that the semiconductor device operates in a state where the power supply noise exceeds the predetermined range.
    Type: Application
    Filed: September 20, 2014
    Publication date: April 2, 2015
    Inventor: Kazuya ENDO
  • Publication number: 20120287081
    Abstract: Provided is a touch sensor panel which can increase the detection sensitivity of a touch relatively readily. The touch sensor panel controller supplies drive electrodes of a touch sensor panel with a high-voltage AC drive signal with its low level set to a negative voltage and drives them. The time of change of a drive waveform supplied to the drive electrodes of the touch sensor panel is shifted relative to the time of change of a drive waveform supplied to a display scan electrode. The touch sensor panel controller uses a charge pump in synchronization with clock signals of more than one phase to produce a high drive voltage to activate drive electrodes of the touch sensor panel, and the clock signals of more than one phase are initialized each time the drive electrode is subjected to AC pulse driving.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 15, 2012
    Inventors: Akihito AKAI, Tatsuya ISHII, Kazuya ENDO, Shinobu NOTOMI, Akihiro KODAMA
  • Publication number: 20090122038
    Abstract: A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
    Type: Application
    Filed: January 7, 2009
    Publication date: May 14, 2009
    Inventors: Toshikazu TACHIBANA, Yoshitaka Iwasaki, Kazuya Endo, Goro Sakamaki
  • Patent number: 7492341
    Abstract: A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: February 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Toshikazu Tachibana, Yoshitaka Iwasaki, Kazuya Endo, Goro Sakamaki
  • Patent number: 7480164
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Patent number: 7342562
    Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI?VCOML)/?t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH?VCI)/?t. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: March 11, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yasushi Kawase, Takesada Akiba, Kazuya Endo, Goro Sakamaki
  • Publication number: 20080049480
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 28, 2008
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20080042951
    Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp(VCI-VCOML)/?t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp(VCOMH?VCI)/?t. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 21, 2008
    Inventors: Yasushi Kawasa, Takesada Akiba, Kazuya Endo, Goro Sakamaki
  • Patent number: 7317627
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: January 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20070296665
    Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI?VCOML)/?t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH?VCI)/?t. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2.
    Type: Application
    Filed: August 24, 2007
    Publication date: December 27, 2007
    Inventors: Yasushi Kawase, Takesada Akiba, Kazuya Endo, Goro Sakamaki
  • Publication number: 20070211508
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: May 8, 2007
    Publication date: September 13, 2007
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota