Abstract: A motion vector detecting device and a motion vector detecting method are provided which can efficiently detect the motion vector even when the chrominance information is dominant in the image. When a mode signal (SM) indicates a chrominance signal mode, an input unit (2) outputs, to an operational unit (1), template block data and search window data in which n pieces of chrominance pixel data (Cb) and n pieces of chrominance pixel data (Cr) alternate with each other. On the basis of the data obtained from the input unit (2), the operational unit (1) calculates three evaluation values (ESa, ESo, ESe) about displacement vectors corresponding to one template block.

Abstract: A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode.

Abstract: A dummy gate electrode is formed just above a channel formation region of a semiconductor substrate by patterning a dummy gate electrode material which is formed on the semiconductor substrate. A dopant is ion-implanted into a surface portion of the semiconductor substrate with the dummy gate electrode used as a mask. Thereby, a source/drain region is formed in self alignment to the dummy gate electrode. A first interlayer insulator is overall formed on the substrate and the dummy gate electrode, and thereafter the first interlayer insulator is subjected to a planarization process to expose a top surface of the dummy gate electrode. A trench is formed on the semiconductor substrate by removing the dummy gate electrode. A gate is made in the trench by forming a buffer dielectric film, a ferroelectric film and a gate electrode material sequentially in this order.

Abstract: A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

Abstract: In a method for fabrication a semiconductor memory device which has a capacitor having a lower electrode, a dielectric film and an upper electrode stacked in this order, after the dielectric film is formed to a desired film thickness, the dielectric film is flattened by removing the dielectric film by a specified amount.

Abstract: After forming a capacitor of a stack type ferroelectric memory device by sequentially patterning an upper electrode, a ferroelectric film and a lower electrode formed above an interlayer insulator film, the capacitor is covered with an oxidation barrier layer. After forming the oxidation barrier layer, the in-process memory device is heat treated at a high temperature in an oxygen-containing atmosphere. The oxidation barrier layer prevents the lower electrode of the capacitor and a barrier metal film between the capacitor and the interlayer insulator film from oxidation during heat treatment. Thus, the occurrence of peelings and hillocks in the lower electrode and the barrier metal film is avoided so that a semiconductor memory has good electrical characteristics and high reliability.

Abstract: In a fabricating method of a semiconductor storage device, a ferroelectric film is formed on a lower electrode, and crystallized. Thereafter, a heat treatment is performed in an atmosphere of hydrogen or a mixture of hydrogen and an inert gas to vanish a defect at the interface between the gate insulating film of a MOS transistor and a silicon substrate. Next, an upper electrode is formed on the ferroelectric film.

Abstract: Disclosed is an image coding method and apparatus for preventing a coding quantity of coding data from being increased when a redundancy between image planes is low. A selector outputs either an optimum motion vector output from a motion vector detecting device or a motion vector output from a motion vector storing section to a real time image coding device for performing coding on the basis of an evaluation value output from the motion vector detecting device. If it is decided, according to the evaluation value, that a redundancy between a reference image plane and a coding object image plane is low, the motion vector is selected so that the coding quantity of the coding data can be prevented from being increased.

Abstract: Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.

Abstract: An evaluation value operation part computes evaluation values of a template block and a search window block in accordance with respective ones of a plurality of predictive modes in parallel with each other, and a candidate vector determination part decides candidate vectors indicating optimum vectors in accordance with the computed evaluation values and on the basis of priority levels from a priority generation part. In accordance with these candidate vectors, an optimum vector decision part decides the optimum vectors for the respective predictive modes. Thus provided is an image coding system which can reduce the amount of codes of motion vectors with excellent picture quality.

Abstract: In a semiconductor storage device, a capacitor section is connected with a drain region of a MOS transistor by means of a polysilicon plug. The capacitor section has a lower electrode, a ferroelectric thin film, and an upper electrode stacked in this order. A TiN barrier metal is placed between the lower electrode and the plug. The lower electrode has a lower film made of a platinum-rhodium alloy and an upper film made of a platinum-rhodium alloy oxide which is in contact with the ferroelectric thin film.

Abstract: Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: To improve the clock delay time and skew. A first resistance body (R1) and a second resistance body (R2) are provided at a terminal end node (N5) of a clock trunk line (1) composed of a doped polysilicon film or the like. Their elements (R1), (R2) are composed of the same film as the clock trunk line (1). Their resistance ratio is set so that the clamp level may be an inverted threshold of first and second local drivers (D2, D3), and the resistance values of both resistance bodies (R1, R2), and the value of interconnection resistance (R) of the clock trunk line (1) are set so that an amplitude of a clock signal at each of the nodes (N3, N4, N5) may be a potential corresponding to 1/2 of its peak-to-peak voltage at the same time.

Abstract: A method for producing a ferroelectric thin film according to the present invention includes the steps of: forming a PbTiO.sub.3 film on an electrode provided on a substrate; and forming a PZT film on the PbTiO.sub.3 film by a CVD method.

Abstract: Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

Abstract: A non-volatile random access memory comprises an MOS transistor having a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, and a pair of diffusion layers formed in the semiconductor substrate; and a ferroelectric capacitor having a bottom electrode connected to one of the diffusion layers of the MOS transistor, a capacitor ferroelectric film formed only on the bottom electrode, and a top electrode formed on the capacitor ferroelectric film; wherein at least side walls of the bottom electrode and the capacitor ferroelectric film are coated with lamination of a diffusion prevention film and a thin insulation film; an upper surface of the capacitor ferroelectric film is contacted with the top electrode; the other diffusion layer of the MOS transistor is connected to a bit line; the gate electrode is connected to a word line; and the top electrode of the ferroelectric capacitor is constituted so as to serve as a drive line.

Abstract: In order to generate zigzag addresses for Discrete Cosine Transformation DCT data arranged in the form of a square matrix, row differentials (.DELTA.y) and column differentials (.DELTA.x) being differentials of row addresses (y) and column addresses (x) are previously stored to be successively read out (steps S12 and S13). The row differentials (.DELTA.y) and the column differentials (.DELTA.x) are added to the row addresses (y) and the column addresses (x) respectively, to newly obtain zigzag addresses (steps S14 and S15). Thus, the amount data to be stored can be reduced. Further, it is possible to further reduce the amount of data to be stored by compressing data through regularity of the row differentials (.DELTA.y) and the column differentials (.DELTA.x).

Abstract: A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value.

Abstract: An information processing system including processors, and an interrupt controller responsive to an interrupt request signal from the processors for executing an interrupt process control of processes carried out by the processors. The interrupt controller includes an interrupt process execution device that does not have a multiple interrupt processing function, and an interrupt acceptance device. The interrupt acceptance device has an interrupt reservation signal input terminal, and responds to an interrupt request signal for making determination whether an interrupt is permitted. If interrupt is permitted, an interrupt request generation signal is applied to a corresponding interrupt request generation signal input terminal of the interrupt process execution device. Each of the processors includes an interrupt request signal output circuit and a processing circuit.