Patents by Inventor Kazuya Nakayama
Kazuya Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6297586Abstract: Disclosed herein are a cold-cathode power switching device and a method of manufacturing the same. The device has a high voltage resistance and can be manufactured with high yield though its element area is large to control large currents. In the method, arrays of miniature emitters are prepared, and the emitter arrays are adhered to a conductive substrate having trenches. The conductive substrate is cut along the trenches, forming a plurality of substrates. The gaps between these substrates are filled with insulating resin. As a result, a multi-module power switching device for controlling large currents is manufactured with high yield. Further, cold-cathode modules, each having a gate pad, are arranged on a cathode electrode made of a conducive substrate, insulating strips are formed on the cathode electrode, gate lines are formed on the insulating strips, and the gate pads are connected to the gate lines. The electrons emitted from the modules can be controlled at a time.Type: GrantFiled: March 5, 1999Date of Patent: October 2, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Nakayama, Tadashi Sakai, Naoshi Sakuma, Tomio Ono
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Patent number: 6236069Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: June 23, 1998Date of Patent: May 22, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 6057636Abstract: The present invention provides a micro power switch comprising a cold cathode for emitting electrons, an anode for capturing the electrons emitted from the cold cathode, and a control electrode for controlling an amount of the electrons emitted from the cold cathode, wherein the cold cathode is made of material having a smaller electron emission barrier than the control electrode, the anode is applied with a positive potential in relation to the cold cathode, and the control electrode is applied with a potential equal to or lower than a potential of the cold cathode.Type: GrantFiled: September 16, 1997Date of Patent: May 2, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Sakai, Tomio Ono, Naoshi Sakuma, Hiromichi Ohashi, Kazuya Nakayama
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Patent number: 6040598Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg [F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [.OMEGA.], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied:.vertline.Vth-Voff.vertline..gtoreq.0.5.multidot.Cg.multidot.Rg.multidot.Type: GrantFiled: March 17, 1998Date of Patent: March 21, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Nakayama, Koichi Sugiyama
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Patent number: 6019209Abstract: A medium or bill reserving apparatus of the invention receives and reserves at least one individually transferred medium or bill, and discharges the reserved media in a batch. The apparatus is formed of an accumulating wheel having an outer surface and a groove portion opened in the outer surface to receive a tip of the medium for holding. The accumulating wheel is rotated from a medium standby position to a medium release position. A clamper is formed in the accumulating wheel to clamp the tip of the medium introduced into the groove portion and to release the medium at the medium release position, and a medium-accumulating section is formed outside the accumulating wheel for accumulating the medium released at the medium-release position.Type: GrantFiled: April 2, 1998Date of Patent: February 1, 2000Assignee: Fuji Electric Co., Ltd.Inventors: Toshio Hara, Hiroharu Yamamoto, Isao Kidokoro, Mamoru Yamagata, Katumi Ooe, Tetuji Kawasaki, Kazuya Nakayama, Yukihiro Takano, Tatuhiko Sonehara, Takanori Yamada
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Patent number: 5793065Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: June 7, 1995Date of Patent: August 11, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 5703383Abstract: A power semiconductor device comprises a plurality of IGBT's, and gate electrodes and source electrodes are alternately arranged. In two adjacent IGBT's, the gate electrode is positioned between two source electrodes, and in the next two adjacent IGBT's, the source electrode is positioned between two gate electrodes. The power semiconductor device is designed to meet conditions of 60 .mu.m.ltoreq.L.sub.G, 5.ltoreq.L.sub.G /L.sub.S, and 1.ltoreq.L.sub.G.sup.2 /(D.sub.B .multidot.W.sub.B).ltoreq.9, where L.sub.G denotes the width of the gate electrode, D.sub.B denotes the depth of the base layer of the first conductivity type, W.sub.B denotes the thickness of that portion of the base layer of the second conductivity type which is sandwiched between the base layer of the first conductivity type and the emitter layer of the first conductivity type, and L.sub.S denotes the distance between these gate electrodes.Type: GrantFiled: April 8, 1996Date of Patent: December 30, 1997Assignee: Kabushiki Kaisha ToshibaInventor: Kazuya Nakayama
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Patent number: 5668194Abstract: This invention relates to a room temperature curing composition for use in various coatings for interior and exterior sidings, automotive bodies, household electrical appliances and plastic substrates and particularly for coatings required to have weather resistance and durability. The room temperature curing composition of this invention comprises an emulsion obtained by a multi-stage polymerization of monomers, said emulsion comprising emulsion particles, the core of which is formed by polymerization of (A) a silyl group-containing vinyl monomer, (B) an alkyl or cycloalkyl methacrylate whose alkyl moiety contains not less than 4 carbon atoms, and (C) a non-hydrophilic vinyl monomer other than (B) and the outer shell of which is formed by polymerization of (A), (B), (C) and (D) a hydrophilic vinyl monomer. The room temperature curing composition of this invention features a high stability of silyl groups it contains and a remarkably improved film-forming property even after prolonged storage.Type: GrantFiled: December 14, 1995Date of Patent: September 16, 1997Assignee: Kanegafuchi Chemical Industry Co., Ltd.Inventors: Naotami Ando, Toshiyuki Masuda, Takanori Hatano, Kazuya Nakayama
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Patent number: 5554862Abstract: In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.Type: GrantFiled: January 19, 1994Date of Patent: September 10, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Mitsuhiko Kitagawa, Kazuya Nakayama, Masakazu Yamaguchi
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Patent number: 5464994Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: August 16, 1994Date of Patent: November 7, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 5463231Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.Type: GrantFiled: December 2, 1994Date of Patent: October 31, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kiminori Watanabe, Akio Nakagawa, Yoshihiro Yamaguchi, Norio Yasuhara, Tomoko Matsudai, Shigeru Hasegawa, Kazuya Nakayama
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Patent number: 5428228Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.Type: GrantFiled: December 10, 1993Date of Patent: June 27, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kiminori Watanabe, Akio Nakagawa, Yoshihiro Yamaguchi, Norio Yasuhara, Tomoko Matsudai, Shigeru Hasegawa, Kazuya Nakayama
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Patent number: 5381026Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: September 16, 1991Date of Patent: January 10, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 5141782Abstract: This invention permits, in a colored galvanized coating using Ti-Zn, Mn-Zn, Ti-Mn-Zn, (Ti, Mn)-(Cu, Ni, Cr)-Zn, etc., to clearly and stably develop yellow, purple, green, blue or other color by controlling the composition of a galvanizing bath and oxidizing conditions. Further, gold, dark red, olive gray and iridecence color which have not yet obtained can be developed. The color development effected by this invention is clearer than conventional. Instead of galvanizing, the spraying process may be adopted. The surface painting on the colored zinc coating is effective.Type: GrantFiled: May 2, 1991Date of Patent: August 25, 1992Assignee: Nippon Mining Co., Ltd.Inventors: Masatoshi Tomita, Susumu Yamamoto, Chikara Tominaga, Kazuya Nakayama
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Patent number: 5022937Abstract: This invention permits, in a colored galvanized coating using Ti--Zn, Mn--Zn, Ti--Mn--Zn, (Ti, Mn)--(Cu, Ni, Cr)--Zn, etc., to clearly and stably develop yellow, purple, green, blue or other color by controlling the composition of a galvanizing bath and oxidizing conditions. Further, gold, dark red, olive gray and iridescence color which have not yet obtained can be developed. The color development effected by this invention is clearer than conventional. Instead of galvanizing, the spraying process may be adopted. The surface painting on the colored zinc coating is effective.Type: GrantFiled: November 3, 1987Date of Patent: June 11, 1991Assignees: Nippon Mining Co., Ltd., Nikko Aen Kabushiki KaishaInventors: Masatoshi Tomita, Susumu Yamamoto, Chikara Tominaga, Kazuya Nakayama