Abstract: A semiconductor device, includes: a substrate having an effective element area on which a functional element is disposed, and a peripheral area that surrounds the effective element area, the substrate having a terminal portion in at least a portion of the peripheral area a first wiring board connected to the substrate via the terminal portion of the substrate; and a drive circuit chip having a drive circuit, and connected to the first wiring board, wherein a thermal conductivity of the first wiring board is equal to or higher than a thermal conductivity of the substrate and of the drive circuit chip.

Abstract: A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.

Abstract: A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.

Abstract: Provided is an electronic device that suppresses an increase in internal pressure while suppressing entry of a foreign material. An electronic module according to the present embodiment has an electronic device, a substrate, a frame, and a cover, a hole portion having a first opening in a first main surface and a second opening in a second main surface and communicating the internal space and the external space, and a component is disposed to face the second opening.

Abstract: According to the disclosure, a relationship of Tgp>Tgf, ?f1<?PCB1, and (Tgp?To)×?PCB1<(Tgf?To)×?f1+(Tgp?Tgf)×?f2 or a relationship of Tgp<Tgf, ?PCB1<?f1, and (Tgf?To)×?f1<(Tgp?To)×?PCB1+(Tgf?Tgp)×?PCB2 is satisfied, where linear expansion coefficients in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate and at a temperature above the glass transition temperature Tgp of the substrate are denoted as ?PCB1 and ?PCB2, respectively, linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame and at a temperature above the glass transition temperature Tgf of the frame are denoted as ?f1 and ?f2, respectively, and a room temperature is denoted as To.

Abstract: According to the disclosure, a relationship of Tgp>Tgf, ?f1<?PCB1, and (Tgp-To) ×?PCB1<(Tgf-To)×?f1+(Tgp-Tgf)×?f2 or a relationship of Tgp<Tgf, ?PCB1<?f1, and (Tgf-To)×?f1<(Tgp-To)×?PCB1+(Tgf-Tgp)×?PCB2 is satisfied, where linear expansion coefficients in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate and at a temperature above the glass transition temperature Tgp of the substrate are denoted as ?PCB1 and ?PCB2, respectively, linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame and at a temperature above the glass transition temperature Tgf of the frame are denoted as ?f1 and ?f2, respectively, and a room temperature is denoted as To.

Abstract: Provided is an electronic device that suppresses an increase in internal pressure while suppressing entry of a foreign material. An electronic module according to the present embodiment has an electronic device, a substrate, a frame, and a cover, a hole portion having a first opening in a first main surface and a second opening in a second main surface and communicating the internal space and the external space, and a component is disposed to face the second opening.

Abstract: The method of the invention includes: placing a base member and a frame member having a thermal expansion coefficient different from a thermal expansion coefficient of the base member in a state in which the base member is stacked with the frame member and a thermosetting adhesive agent is interposed between the base member and the frame member; adhering the base member and the frame member by heating the base member, the frame member, and the adhesive agent from the state to a temperature equal to or higher than a curing temperature of the adhesive agent; and cooling the base member and the frame member from the curing temperature. The frame member in the state is warped so that a flatness error of the frame member after having been cooled becomes smaller than that in a case where the frame member is flat in the state.

Abstract: Provided is an electronic component including: a base member; an electronic device fixed on the base member; and a lid member arranged over the electronic device and fixed on the base member. A primary material of the lid member is a crystal quartz, the lid member has two primary faces opposing to the electronic device and four side faces, and each of the four side faces is a wet-etched face that is not parallel to an optical axis of the crystal quartz.

Abstract: An optical member includes a first region and a second region constituting an interface with an adhesive member. The first region is disposed outside the second region in a second direction intersecting a first direction. An adhesive force generated at an interface between the first region and the adhesive member is smaller than an adhesive force generated at an interface between the second region and the adhesive member.

Abstract: Provided is an electronic component including: a base member; an electronic device fixed on the base member; and a lid member arranged over the electronic device and fixed on the base member. A primary material of the lid member is a crystal quartz, the lid member has two primary faces opposing to the electronic device and four side faces, and each of the four side faces is a wet-etched face that is not parallel to an optical axis of the crystal quartz.

Abstract: An optical member includes a first region and a second region constituting an interface with an adhesive member. The first region is disposed outside the second region in a second direction intersecting a first direction. An adhesive force generated at an interface between the first region and the adhesive member is smaller than an adhesive force generated at an interface between the second region and the adhesive member.

Abstract: A mounting member includes a plurality of internal connecting portions, each of which is electrically connected to an electronic device, and a plurality of external connecting portions, each of which is soldered, wherein the plurality of external connecting portions include a first connecting portion in communication with at least any of the plurality of internal connecting portions, and a second connecting portion different from the first connecting portion, and surfaces of the first connecting portion and the second connecting portion include gold layers, and a thickness of the gold layer of the second connecting portion is smaller than a thickness of the gold layer of the first connecting portion.

Abstract: A package includes a base body to which an electronic device is fixed, a lid body that faces the electronic device, and a frame body that encloses at least one of a space between the electronic device and the lid body, and the electronic device. The frame body has a first portion located at a side of an inner edge of the frame body with respect to an outer edge of the base body, and a second portion located at a side of an outer edge of the frame body with respect to the outer edge of the base body, in an X direction from the inner edge of the frame body toward the outer edge of the frame body.

Abstract: A mounting member includes a plurality of internal connecting portions, each of which is electrically connected to an electronic device, and a plurality of external connecting portions, each of which is soldered, wherein the plurality of external connecting portions include a first connecting portion in communication with at least any of the plurality of internal connecting portions, and a second connecting portion different from the first connecting portion, and surfaces of the first connecting portion and the second connecting portion include gold layers, and a thickness of the gold layer of the second connecting portion is smaller than a thickness of the gold layer of the first connecting portion.

Abstract: The method of the invention includes: placing a base member and a frame member having a thermal expansion coefficient different from a thermal expansion coefficient of the base member in a state in which the base member is stacked with the frame member and a thermosetting adhesive agent is interposed between the base member and the frame member; adhering the base member and the frame member by heating the base member, the frame member, and the adhesive agent from the state to a temperature equal to or higher than a curing temperature of the adhesive agent; and cooling the base member and the frame member from the curing temperature. The frame member in the state is warped so that a flatness error of the frame member after having been cooled becomes smaller than that in a case where the frame member is flat in the state.

Abstract: A package includes a base body to which an electronic device is fixed, a lid body that faces the electronic device, and a frame body that encloses at least one of a space between the electronic device and the lid body, and the electronic device. The frame body has a first portion located at a side of an inner edge of the frame body with respect to an outer edge of the base body, and a second portion located at a side of an outer edge of the frame body with respect to the outer edge of the base body, in an X direction from the inner edge of the frame body toward the outer edge of the frame body.

Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.

Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.

Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.