Patents by Inventor Kazuya Notsu

Kazuya Notsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7238973
    Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain induction porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: July 3, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Kiyofumi Sakaguchi, Nobuhiko Sato, Hajime Ikeda, Shoji Nishida
  • Publication number: 20060124961
    Abstract: A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made of the same material as the silicon layer of the strained semiconductor layer. The structure is separated into two parts at the separation layer. When the residue of the separation layer and the SiGe layer are removed, and the surface is planarized by hydrogen annealing, an Si substrate having a strained silicon layer on the uppermost surface is obtained.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 15, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kiyofumi Sakaguchi, Kazuya Notsu, Kazutaka Momoi, Nobuhiko Sato
  • Publication number: 20060113635
    Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain induction porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 1, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kazuya Notsu, Kiyofumi Sakaguchi, Nobuhiko Sato, Hajime Ikeda, Shoji Nishida
  • Patent number: 7008701
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15?), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10?). This first substrate (10?) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: March 7, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Publication number: 20060035447
    Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 16, 2006
    Inventors: Hajime Ikeda, Kazuya Notsu, Nobuhiko Sato, Shoji Nishida
  • Patent number: 6828214
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: December 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Publication number: 20040241398
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Application
    Filed: July 6, 2004
    Publication date: December 2, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Publication number: 20020146892
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 10, 2002
    Inventors: Kazuya Notsu, Nobuhiko Sato