Patents by Inventor Kazuya Okubo

Kazuya Okubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8889505
    Abstract: A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuya Okubo, Nobuyuki Ohtsuka
  • Publication number: 20140326550
    Abstract: A brake disc is provided capable of effectively reducing the generation of noise such as brake noise by making specifications relating to lightening holes different from each other between two brake disc plates. In the brake disc, two brake disc plates are laminated so as to slide on each other by vibration during braking, and specifications relating to one or more selected from lightening holes, plate thickness, diameter, and warpage are made different from each other between the brake disc plates. In addition, lightening holes are formed on at least one of the brake disc plates, and one or more specifications selected from the number of lightening holes, the shapes of the lightening holes, the sizes of the lightening holes, and the arrangement positions of the lightening holes are made different from each other between the brake disc plates.
    Type: Application
    Filed: February 16, 2012
    Publication date: November 6, 2014
    Applicants: THE DOSHISHA, SUNSTAR ENGINEERING INC.
    Inventors: Toru Fujii, Kazuya Okubo, Kiyotaka Obunai, Yoshihisa Kubota, Hideaki Okada, Tsuyoshi Nakatsuji
  • Publication number: 20140100306
    Abstract: The invention provides a polyphenylene sulfide resin composition including: 1 to 100 parts by weight of an olefin elastomer (B); and 0.01 to 10 parts by weight of a carboxylic acid amide wax mixture (C), relative to 100 parts by weight of a polyphenylene sulfide resin (A), wherein the carboxylic acid amide wax mixture (C) is obtained by adding 0.01 to 5 parts by weight of an antioxidant to 100 parts by weight of a carboxylic acid amide wax produced by reaction of a higher aliphatic monocarboxylic acid, a polybasic acid and a diamine.
    Type: Application
    Filed: June 22, 2012
    Publication date: April 10, 2014
    Applicant: Toray Industries, Inc.
    Inventors: Kazuya Okubo, Atsushi Ishio, Yuki Ota
  • Publication number: 20140004711
    Abstract: A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-
    Type: Application
    Filed: September 4, 2013
    Publication date: January 2, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Kazuya Okubo, Nobuyuki Ohtsuka
  • Patent number: 8575704
    Abstract: A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: November 5, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Akiyoshi Hatada, Akira Katakami, Yuka Kase, Kazuya Okubo
  • Patent number: 8551832
    Abstract: A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuya Okubo, Nobuyuki Ohtsuka
  • Patent number: 8536708
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Publication number: 20120326315
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Patent number: 8338953
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Publication number: 20120261760
    Abstract: A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.
    Type: Application
    Filed: March 8, 2012
    Publication date: October 18, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Haneda, Akiyoshi Hatada, Akira Katakami, Yuka Kase, Kazuya Okubo
  • Patent number: 8148262
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuya Okubo, Yusuke Morisaki, Youichi Momiyama
  • Publication number: 20110241211
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Hisaya SAKAI, Hirofumi WATATANI, Kazuya OKUBO
  • Patent number: 8030207
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Patent number: 7984453
    Abstract: An availability system is provided that includes a hierarchy of controllers for providing event notifications relating to availability of components of a scalable MPP system. A controller receives a subscription from a child controller that identifies an event type and a generator. The controller stores in a subscription store an indication that the subscription has been received from the child controller. When a parent controller has not yet been notified of a subscription with a matching event type and generator as indicated by the subscription store, the controller sends the subscription to the parent controller. When the parent controller has already been notified of a subscription with a matching event type and generator as indicated by the subscription store, the controller suppresses the sending of the subscription to the parent controller.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: July 19, 2011
    Assignee: Cray Inc.
    Inventors: Gail A. Alverson, Robert L. Alverson, Daniel C. Duval, Eric A. Hoffman, Laurence S. Kaplan, Matthew Kelly, Kazuya Okubo, Mark Swan, Asaph Zemach
  • Publication number: 20110169105
    Abstract: A method of manufacturing a semiconductor device includes forming a polysilicon pattern, source/drain, and side-wall spacer, epitaxially growing silicide films on the source/drain, epitaxially growing silicon films selectively on the silicide film, removing the polysilicon pattern, forming a gate insulating film and gate electrode.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 14, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kazuya OKUBO
  • Publication number: 20100330812
    Abstract: A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-
    Type: Application
    Filed: June 21, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Kazuya Okubo, Nobuyuki Ohtsuka
  • Publication number: 20100330764
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Kazuya Okubo, Yusuke Morisaki, Youichi Momiyama
  • Publication number: 20090316332
    Abstract: A thin film capacitor is disposed over a semiconductor substrate. The thin film capacitor includes a lower electrode at least an upper surface of which is made of amorphous or microcrystalline metal, a dielectric film disposed over the lower electrode, and an upper electrode disposed over the dielectric film.
    Type: Application
    Filed: February 5, 2009
    Publication date: December 24, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kazuya OKUBO, Shinichi AKIYAMA, Kenji NAITO, Makoto NAKAMURA
  • Patent number: 7592256
    Abstract: A method of forming a tungsten film on a surface of an object to be processed in a vessel capable of being vacuumized, includes the steps of forming a tungsten film by alternately repeating a reduction gas supplying process for supplying a reduction gas and a tungsten gas supplying process for supplying a tungsten-containing gas with an intervening purge process therebetween for supplying an inert gas while vacuumizing the vessel. A reduction gas supplying period of a reduction gas supplying process among the repeated reduction gas supplying processes is set to be longer than that of the remaining reduction gas supplying processes.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 22, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kazuya Okubo, Mitsuhiro Tachibana, Cheng Fang, Kohichi Sato, Hotaka Ishizuka
  • Publication number: 20090085130
    Abstract: The present invention relates to a semiconductor device comprising a semiconductor substrate (1), a gate insulator formed on this substrate, such as a gate oxide film (2), and a gate electrode (3) formed on the insulator. The gate electrode (3) has a metallic compound film (3a). This metallic compound film (3a) is formed by CVD using a material containing a metal carbonyl, e.g., W(CO)6 gas, and at least one of a Si-containing gas and a N-containing gas. The work function of the metallic compound film (3a) thus formed is controllable by the Si and/or N content of the film.
    Type: Application
    Filed: January 28, 2005
    Publication date: April 2, 2009
    Inventors: Kenji Suzuki, Gishi Chung, Kazuya Okubo