Patents by Inventor Kazuya Uejima

Kazuya Uejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456665
    Abstract: An electronic system device includes a semiconductor device and a power generating device for generating a power supply voltage. The semiconductor device includes a control circuit coupled with the power generating device via a power supply node, and a substrate-biased control circuit coupled with the control circuit. The electronic system device includes a DC-DC converter, and a switch arranged between the power supply nodes and the DC-DC converter. The control circuit sets the switch to an ON state after receiving the power supply voltage. The DC-DC converter receives the power supply voltage after the switch is controlled to the ON state. The substrate bias control circuit supplies a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Hashimoto, Kazuya Uejima
  • Publication number: 20220264450
    Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Inventors: Shiro KAMOHARA, Akira TANABE, Kazuya UEJIMA, Jun UEHARA, Kazuya OKUYAMA
  • Patent number: 11392192
    Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuya Uejima
  • Patent number: 11391389
    Abstract: The semiconductor device controls the first circuit for supplying/stopping the current supplied by a DC power supply to the latching solenoid consisting of a coil and a movable iron core and a permanent magnet, the current is measured based on the input from the current detection circuit. The semiconductor device includes a control circuit having a low power dissipation mode in which the leakage current is reduced, and a normal operation mode. The control circuit maintains the low power consumption mode when no current is flowing through the coil, when a current is flowing through the coil maintains the normal operation mode, further, the movable iron core It comprises a control circuit configured to detect the inflection point of the current detected by the current detection circuit when leaving the permanent magnet.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shiro Kamohara, Kazuya Uejima
  • Publication number: 20220189998
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Application
    Filed: March 4, 2022
    Publication date: June 16, 2022
    Inventors: Kazuya UEJIMA, Kazuhiro KOUDATE
  • Patent number: 11296118
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Uejima, Kazuhiro Koudate
  • Publication number: 20210116951
    Abstract: An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 22, 2021
    Inventors: Akira TANABE, Kazuya UEJIMA
  • Publication number: 20210111194
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Kazuya UEJIMA, Kazuhiro KOUDATE
  • Patent number: 10879271
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Uejima, Kazuhiro Koudate
  • Publication number: 20200321861
    Abstract: An electronic system device includes a semiconductor device and a power generating device for generating a power supply voltage. The semiconductor device includes a control circuit coupled with the power generating device via a power supply node, and a substrate-biased control circuit coupled with the control circuit. The electronic system device includes a DC-DC converter, and a switch arranged between the power supply nodes and the DC-DC converter. The control circuit sets the switch to an ON state after receiving the power supply voltage. The DC-DC converter receives the power supply voltage after the switch is controlled to the ON state. The substrate bias control circuit supplies a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.
    Type: Application
    Filed: March 23, 2020
    Publication date: October 8, 2020
    Inventors: Kazuya HASHIMOTO, Kazuya UEJIMA
  • Publication number: 20200313000
    Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.
    Type: Application
    Filed: November 14, 2017
    Publication date: October 1, 2020
    Inventors: Kazuya UEJIMA, Shiro KAMOHARA, Michio ONDA, Takashi HASE, Tatsuo NISHINO
  • Publication number: 20200309282
    Abstract: The semiconductor device controls the first circuit for supplying/stopping the current supplied by a DC power supply to the latching solenoid consisting of a coil and a movable iron core and a permanent magnet, the current is measured based on the input from the current detection circuit. The semiconductor device includes a control circuit having a low power dissipation mode in which the leakage current is reduced, and a normal operation mode. The control circuit maintains the low power consumption mode when no current is flowing through the coil, when a current is flowing through the coil maintains the normal operation mode, further, the movable iron core It comprises a control circuit configured to detect the inflection point of the current detected by the current detection circuit when leaving the permanent magnet.
    Type: Application
    Filed: March 16, 2020
    Publication date: October 1, 2020
    Inventors: Shiro KAMOHARA, Kazuya UEJIMA
  • Publication number: 20200133381
    Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 30, 2020
    Inventor: Kazuya UEJIMA
  • Publication number: 20190369688
    Abstract: A semiconductor device can stably execute a start-up operation in a simple manner. The semiconductor device is driven by a power supply voltage generated by a power generation device. the semiconductor device includes a load circuit for receiving the power supply voltage from a power supply node, a switch provided between the power supply node and the load circuit, a first capacitor connected to the power supply node in parallel with the switch, and a switch control circuit for controlling the switch based on a voltage level of the power supply node.
    Type: Application
    Filed: May 8, 2019
    Publication date: December 5, 2019
    Inventors: Akira TANABE, Kazuya UEJIMA
  • Publication number: 20190319047
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Application
    Filed: March 22, 2019
    Publication date: October 17, 2019
    Inventors: Kazuya UEJIMA, Kazuhiro KOUDATE
  • Publication number: 20190187737
    Abstract: There is a need to ensure operations at a predetermined operating frequency when a temperature changes in an operating state. A semiconductor device includes: a bias-applied portion applied with a substrate bias; a temperature sensor to detect a temperature; and a substrate bias generator to apply the bias-applied portion with a substrate bias corresponding to the temperature detected by the temperature sensor. The bias-applied portion, while applied with a substrate bias by the substrate bias generator, shifts between an operating state and a stopped state. The substrate bias generator applies the bias-applied portion with a substrate bias configured so as not to cause an upper limit of an operating frequency for the bias-applied portion to be smaller than a predetermined value under condition of the temperature detected by the temperature sensor.
    Type: Application
    Filed: October 29, 2018
    Publication date: June 20, 2019
    Inventors: Masaharu MATSUDAIRA, Takashi HASE, Akira TANABE, Kazuya UEJIMA
  • Patent number: 9892788
    Abstract: It is required to store data to be stored for a holding period required for this data and then erase the data while suppressing power consumption. A memory device 10 to solve such a problem has the following configuration. The memory device 10 includes an ReRAM (resistance random access memory) 100 and a storage controller 101. The storage controller 101 performs control to store, in a storing condition according to a holding period required for data to be stored, the data in the ReRAM 100.
    Type: Grant
    Filed: July 30, 2016
    Date of Patent: February 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuya Uejima
  • Publication number: 20170290553
    Abstract: In order to appropriately set a condition for measurement of a sensor for measuring an object to be measured in accordance with a change of an external index that can affect the object to be measured, a sensor system includes first and second sensors, a determination unit for outputting a detection signal when a measurement result of the first sensor satisfies a predetermined condition, a measurement condition storage unit for storing a condition for measurement of the second sensor, and a control unit for performing measurement by the second sensor separately from measurement in accordance with the condition for measurement, when having received the detection signal, and for updating the condition for measurement of the second sensor stored in the measurement condition storage unit based on a result of the performed measurement.
    Type: Application
    Filed: March 23, 2017
    Publication date: October 12, 2017
    Inventors: Masaharu Matsudaira, Takashi Hase, Akira Tanabe, Kazuya Uejima
  • Publication number: 20170076781
    Abstract: It is required to store data to be stored for a holding period required for this data and then erase the data while suppressing power consumption. A memory device 10 to solve such a problem has the following configuration. The memory device 10 includes an ReRAM (resistance random access memory) 100 and a storage controller 101. The storage controller 101 performs control to store, in a storing condition according to a holding period required for data to be stored, the data in the ReRAM 100.
    Type: Application
    Filed: July 30, 2016
    Publication date: March 16, 2017
    Inventor: Kazuya UEJIMA
  • Patent number: 9577095
    Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Uejima, Hidetatsu Nakamura, Akihito Sakakidani, Eiichirou Watanabe