Patents by Inventor Kazuya Uejima
Kazuya Uejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742356Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: GrantFiled: March 4, 2022Date of Patent: August 29, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Kazuhiro Koudate
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Patent number: 11665640Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.Type: GrantFiled: February 17, 2021Date of Patent: May 30, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shiro Kamohara, Akira Tanabe, Kazuya Uejima, Jun Uehara, Kazuya Okuyama
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Patent number: 11604484Abstract: An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.Type: GrantFiled: October 12, 2020Date of Patent: March 14, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Tanabe, Kazuya Uejima
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Publication number: 20220406936Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.Type: ApplicationFiled: August 29, 2022Publication date: December 22, 2022Inventors: Kazuya UEJIMA, Michio ONDA, Takashi HASE, Tatsuo NISHINO, Shiro KAMOHARA
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Patent number: 11456665Abstract: An electronic system device includes a semiconductor device and a power generating device for generating a power supply voltage. The semiconductor device includes a control circuit coupled with the power generating device via a power supply node, and a substrate-biased control circuit coupled with the control circuit. The electronic system device includes a DC-DC converter, and a switch arranged between the power supply nodes and the DC-DC converter. The control circuit sets the switch to an ON state after receiving the power supply voltage. The DC-DC converter receives the power supply voltage after the switch is controlled to the ON state. The substrate bias control circuit supplies a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.Type: GrantFiled: March 23, 2020Date of Patent: September 27, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Hashimoto, Kazuya Uejima
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Publication number: 20220264450Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Inventors: Shiro KAMOHARA, Akira TANABE, Kazuya UEJIMA, Jun UEHARA, Kazuya OKUYAMA
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Patent number: 11392192Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.Type: GrantFiled: September 18, 2019Date of Patent: July 19, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Kazuya Uejima
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Patent number: 11391389Abstract: The semiconductor device controls the first circuit for supplying/stopping the current supplied by a DC power supply to the latching solenoid consisting of a coil and a movable iron core and a permanent magnet, the current is measured based on the input from the current detection circuit. The semiconductor device includes a control circuit having a low power dissipation mode in which the leakage current is reduced, and a normal operation mode. The control circuit maintains the low power consumption mode when no current is flowing through the coil, when a current is flowing through the coil maintains the normal operation mode, further, the movable iron core It comprises a control circuit configured to detect the inflection point of the current detected by the current detection circuit when leaving the permanent magnet.Type: GrantFiled: March 16, 2020Date of Patent: July 19, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shiro Kamohara, Kazuya Uejima
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Publication number: 20220189998Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: ApplicationFiled: March 4, 2022Publication date: June 16, 2022Inventors: Kazuya UEJIMA, Kazuhiro KOUDATE
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Patent number: 11296118Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: GrantFiled: December 22, 2020Date of Patent: April 5, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Kazuhiro Koudate
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Publication number: 20210116951Abstract: An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.Type: ApplicationFiled: October 12, 2020Publication date: April 22, 2021Inventors: Akira TANABE, Kazuya UEJIMA
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Publication number: 20210111194Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Kazuya UEJIMA, Kazuhiro KOUDATE
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Patent number: 10879271Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: GrantFiled: March 22, 2019Date of Patent: December 29, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Kazuhiro Koudate
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Publication number: 20200321861Abstract: An electronic system device includes a semiconductor device and a power generating device for generating a power supply voltage. The semiconductor device includes a control circuit coupled with the power generating device via a power supply node, and a substrate-biased control circuit coupled with the control circuit. The electronic system device includes a DC-DC converter, and a switch arranged between the power supply nodes and the DC-DC converter. The control circuit sets the switch to an ON state after receiving the power supply voltage. The DC-DC converter receives the power supply voltage after the switch is controlled to the ON state. The substrate bias control circuit supplies a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.Type: ApplicationFiled: March 23, 2020Publication date: October 8, 2020Inventors: Kazuya HASHIMOTO, Kazuya UEJIMA
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Publication number: 20200309282Abstract: The semiconductor device controls the first circuit for supplying/stopping the current supplied by a DC power supply to the latching solenoid consisting of a coil and a movable iron core and a permanent magnet, the current is measured based on the input from the current detection circuit. The semiconductor device includes a control circuit having a low power dissipation mode in which the leakage current is reduced, and a normal operation mode. The control circuit maintains the low power consumption mode when no current is flowing through the coil, when a current is flowing through the coil maintains the normal operation mode, further, the movable iron core It comprises a control circuit configured to detect the inflection point of the current detected by the current detection circuit when leaving the permanent magnet.Type: ApplicationFiled: March 16, 2020Publication date: October 1, 2020Inventors: Shiro KAMOHARA, Kazuya UEJIMA
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Publication number: 20200313000Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.Type: ApplicationFiled: November 14, 2017Publication date: October 1, 2020Inventors: Kazuya UEJIMA, Shiro KAMOHARA, Michio ONDA, Takashi HASE, Tatsuo NISHINO
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Publication number: 20200133381Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.Type: ApplicationFiled: September 18, 2019Publication date: April 30, 2020Inventor: Kazuya UEJIMA
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Publication number: 20190369688Abstract: A semiconductor device can stably execute a start-up operation in a simple manner. The semiconductor device is driven by a power supply voltage generated by a power generation device. the semiconductor device includes a load circuit for receiving the power supply voltage from a power supply node, a switch provided between the power supply node and the load circuit, a first capacitor connected to the power supply node in parallel with the switch, and a switch control circuit for controlling the switch based on a voltage level of the power supply node.Type: ApplicationFiled: May 8, 2019Publication date: December 5, 2019Inventors: Akira TANABE, Kazuya UEJIMA
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Publication number: 20190319047Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: ApplicationFiled: March 22, 2019Publication date: October 17, 2019Inventors: Kazuya UEJIMA, Kazuhiro KOUDATE
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Publication number: 20190187737Abstract: There is a need to ensure operations at a predetermined operating frequency when a temperature changes in an operating state. A semiconductor device includes: a bias-applied portion applied with a substrate bias; a temperature sensor to detect a temperature; and a substrate bias generator to apply the bias-applied portion with a substrate bias corresponding to the temperature detected by the temperature sensor. The bias-applied portion, while applied with a substrate bias by the substrate bias generator, shifts between an operating state and a stopped state. The substrate bias generator applies the bias-applied portion with a substrate bias configured so as not to cause an upper limit of an operating frequency for the bias-applied portion to be smaller than a predetermined value under condition of the temperature detected by the temperature sensor.Type: ApplicationFiled: October 29, 2018Publication date: June 20, 2019Inventors: Masaharu MATSUDAIRA, Takashi HASE, Akira TANABE, Kazuya UEJIMA