Patents by Inventor Kazuyoshi Shoji
Kazuyoshi Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7856072Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: GrantFiled: June 10, 2009Date of Patent: December 21, 2010Assignee: Elpida Memory, Inc.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Publication number: 20090245424Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: ApplicationFiled: June 10, 2009Publication date: October 1, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Patent number: 7558336Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: GrantFiled: November 8, 2004Date of Patent: July 7, 2009Assignee: Elpida Memory, Inc.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Patent number: 7372741Abstract: A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.Type: GrantFiled: June 29, 2006Date of Patent: May 13, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Publication number: 20080040081Abstract: In the simulation method of the present invention; one parameter is first selected from a plurality of parameters that relate to input/output characteristics. Next, regarding setting lines provided in a file for setting necessary choices from among a plurality of choices for a selected parameter, it is determined to either set choices by means of comment symbols that cause non-execution of the relevant lines, or set choices by means of identification codes, which are identifiers common to chips in which the same choice are to be set. When choices are to be set by means of comment symbols, the comment symbols of the setting lines of the necessary choices among the plurality of choices are deleted to make these setting lines effective. Alternatively, when choices are to be set by means of identification codes, the identification codes included in setting lines are rewritten to information for setting to the necessary choices. Finally, the simulation is executed.Type: ApplicationFiled: February 16, 2007Publication date: February 14, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yoji NISHIO, Seiji Funaba, Yurika Aoki, Kazuyoshi Shoji, Koji Matsuo, Mariko Otsuka, Ryuichi Ikematsu, Sadahiro Nonoyama, Kae Fujii
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Publication number: 20060262605Abstract: A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.Type: ApplicationFiled: June 29, 2006Publication date: November 23, 2006Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 7099199Abstract: A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.Type: GrantFiled: May 4, 2004Date of Patent: August 29, 2006Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 7020028Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: GrantFiled: May 4, 2004Date of Patent: March 28, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Publication number: 20060018407Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: ApplicationFiled: November 8, 2004Publication date: January 26, 2006Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Publication number: 20040202019Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: ApplicationFiled: May 4, 2004Publication date: October 14, 2004Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Publication number: 20040202025Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: ApplicationFiled: May 4, 2004Publication date: October 14, 2004Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6791882Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: GrantFiled: June 21, 2002Date of Patent: September 14, 2004Assignee: Renesas Technology Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6747902Abstract: A nonvolatile memory apparatus contains plural memories, at least one of which is a nonvolatile memory, and a processing unit. Data input/output (I/O) terminals of the memories and processing unit are mutually coupled by a bus. When the nonvolatile memory is brought into an erasing mode by the processing unit, it becomes electrically isolated as a result of freeing the connection of the I/O terminal thereof during the erase operation. Accordingly, the processing unit is capable of accessing other memories via the bus where information can then be transferred/received between other memory devices and, otherwise, with the input/output port of the system. Control by the processing unit requires a relatively short time during which the erasing commencement is instructed so as to minimize interruption of the throughput capability of the system. Following the designation of an erasing mode, a data polling mode is designated.Type: GrantFiled: June 21, 2002Date of Patent: June 8, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Publication number: 20030002347Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: ApplicationFiled: June 21, 2002Publication date: January 2, 2003Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Publication number: 20020176282Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: ApplicationFiled: June 21, 2002Publication date: November 28, 2002Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6438036Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.Type: GrantFiled: April 10, 2001Date of Patent: August 20, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Publication number: 20010030889Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a VCC power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the VCC power source is applied to a control gate electrode.Type: ApplicationFiled: April 10, 2001Publication date: October 18, 2001Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6259629Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: October 19, 1999Date of Patent: July 10, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6181600Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 29, 1999Date of Patent: January 30, 2001Assignees: Hitachi, Ltd, Hitachi ULSI Engineering Corporation, Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
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Patent number: 6157576Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: September 10, 1999Date of Patent: December 5, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume