Patents by Inventor Kazuyoshi Shoji
Kazuyoshi Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6016273Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: September 27, 1996Date of Patent: January 18, 2000Assignee: Hitachi, Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5991200Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 6, 1995Date of Patent: November 23, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5959894Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 17, 1998Date of Patent: September 28, 1999Assignees: Hitachi, Ltd., Hitachi USLI Engineering Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5949715Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: September 27, 1996Date of Patent: September 7, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5917752Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 1, 1995Date of Patent: June 29, 1999Assignees: Hitachi, Ltd., Hitachi VSLI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5844842Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: May 26, 1994Date of Patent: December 1, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5781476Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.Type: GrantFiled: June 1, 1995Date of Patent: July 14, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
-
Patent number: 5315547Abstract: In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.Type: GrantFiled: October 13, 1992Date of Patent: May 24, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuyoshi Shoji, Tadashi Muto, Yasurou Kubota, Koichi Seki, Kazuto Izawa, Shinji Nabetani, deceased
-
Patent number: 5097446Abstract: A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.Type: GrantFiled: May 23, 1989Date of Patent: March 17, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuyoshi Shoji, Takaaki Hagiwara, Tadashi Muto, Shun-ichi Saeki, Yasurou Kubota, Kazuto Izawa, Yoshiaki Kamigaki, Shin-ichi Minami, Yuko Nabetani