Patents by Inventor Kazuyuki Tomida
Kazuyuki Tomida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11961885Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.Type: GrantFiled: September 13, 2022Date of Patent: April 16, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Tetsuo Gocho, Yuzo Fukuzaki, Shinichi Miyake, Kazuyuki Tomida
-
Publication number: 20240120353Abstract: A solid-state imaging device (200) includes a photoelectric conversion device (211), a current-voltage conversion circuit (310), and an output circuit. The photoelectric conversion device (211) performs photoelectric conversion of incident light. The current-voltage conversion circuit (310) includes a first transistor (311) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor (311) and generates an output signal based on the voltage signal.Type: ApplicationFiled: January 28, 2022Publication date: April 11, 2024Inventors: KATSUHIKO HANZAWA, SHINICHI MIYAKE, KAZUYUKI TOMIDA
-
Publication number: 20240113120Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Applicant: SONY GROUP CORPORATIONInventors: Hidetoshi Oishi, Koichi Matsumoto, Kazuyuki TOMIDA
-
Publication number: 20240072093Abstract: A solid-state imaging element (200) according to the present disclosure includes a light receiving substrate (201) and a circuit board (202). The light receiving substrate (201) includes a plurality of light receiving circuits (211) in which photoelectric conversion elements are provided. The circuit board (202) is bonded to the light receiving substrate (201) and includes a plurality of address event detection circuits (231) that respectively detects voltage changes output from the photoelectric conversion elements of the plurality of light receiving circuits (211). The circuit board (202) includes a first element region (501) and a second element region (502). In the first element region (501), a first transistor (T1) driven by a first voltage (VDD1) is arranged. In the second element region (502), a second transistor (T2) driven by a second voltage (VDD2) lower than the first voltage (VDD1) is arranged.Type: ApplicationFiled: December 20, 2021Publication date: February 29, 2024Inventors: SHINICHI MIYAKE, KAZUYUKI TOMIDA, ATSUMI NIWA
-
Publication number: 20240064433Abstract: The present technology relates to an imaging element and an imaging device that facilitate miniaturization of pixels. The first substrate including a plurality of detection pixels that generates a voltage signal corresponding to a logarithmic value of a photocurrent, and the second substrate including a detection circuit that detects whether the change amount of the voltage signal of a detection pixel indicated by an inputted selection signal among the plurality of detection pixels exceeds a predetermined threshold or not are stacked, and an element constituting the detection circuit is disposed in each of a first region on a back surface side and a second region on a front surface side of the second substrate. The present technology can be applied to, for example, an imaging element that detects an address event for each pixel.Type: ApplicationFiled: December 28, 2021Publication date: February 22, 2024Inventors: SHINICHI MIYAKE, KAZUYUKI TOMIDA, ATSUMI NIWA
-
Patent number: 11887984Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.Type: GrantFiled: April 7, 2021Date of Patent: January 30, 2024Assignee: Sony Group CorporationInventors: Hidetoshi Oishi, Koichi Matsumoto, Kazuyuki Tomida
-
Publication number: 20230326966Abstract: A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.Type: ApplicationFiled: June 6, 2023Publication date: October 12, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kazuyuki TOMIDA
-
Patent number: 11710769Abstract: A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.Type: GrantFiled: August 13, 2019Date of Patent: July 25, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kazuyuki Tomida
-
Patent number: 11563086Abstract: To further reduce contact resistance when a current or a voltage is taken out from a metal layer. A conductive structure including: an insulating layer; a metal layer provided on one surface of the insulating layer to protrude in a thickness direction of the insulating layer; and a two-dimensional material layer provided along outer shapes of the metal layer and the insulating layer from a side surface of the metal layer to the one surface of the insulating layer.Type: GrantFiled: January 22, 2019Date of Patent: January 24, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kazuyuki Tomida
-
Publication number: 20230006042Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Tetsuo GOCHO, Yuzo FUKUZAKI, Shinichi MIYAKE, Kazuyuki TOMIDA
-
Publication number: 20220353449Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.Type: ApplicationFiled: June 22, 2020Publication date: November 3, 2022Inventors: DAISUKE ITO, KAZUYUKI TOMIDA, MASAKI HANEDA, TSUYOSHI SUZUKI, TAKAAKI MINAMI
-
Patent number: 11476329Abstract: A semiconductor device includes a base, a first FET that includes at least two laminated channel structure portions, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.Type: GrantFiled: June 18, 2019Date of Patent: October 18, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Tetsuo Gocho, Yuzo Fukuzaki, Shinichi Miyake, Kazuyuki Tomida
-
Patent number: 11296215Abstract: [Object] To stably form a low-resistance electrical coupling between a metal and a semiconductor. [Solution] An electrical coupling structure includes: a semiconductor layer; a metal layer; and an intermediate layer that is held between the semiconductor layer and the metal layer, and includes an insulating layer provided on the semiconductor layer side and a two-dimensional material layer provided on the metal layer side.Type: GrantFiled: June 19, 2018Date of Patent: April 5, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Kazuyuki Tomida
-
Publication number: 20220059669Abstract: There is provided a semiconductor device including a channel portion, and a gate electrode provided on a side opposite to the channel portion with a gate insulating film interposed between the gate electrode and the channel portion, in which the gate insulating film incudes a first portion having a first transition metal oxide, and a second portion having a second transition metal oxide and cation species and having a concentration of the cation species different from the first portion.Type: ApplicationFiled: November 29, 2019Publication date: February 24, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kazuyuki TOMIDA
-
Publication number: 20210280673Abstract: A semiconductor device includes a base, a first FET 10n that includes at least two channel structure portions 11n laminated, the channel structure portions 11n each including a channel portion 13n having a nanowire structure 12n, a gate insulation film, and a gate electrode 27n, and a second FET 20n that includes a channel forming layer 23n, a gate insulation layer, and a gate electrode 27n. The first FET 10n and the second FET 20n are provided above the base. The channel portions 13n of the first FET 10n are disposed apart from each other in a laminating direction of the channel structure portions 11n. Assuming that each of a distance between the channel portions 13n of the first FET 10n is a distance L1 and that a thickness of the gate insulation layer of the second FET 20n is a thickness T2, T2?(L1/2) is satisfied.Type: ApplicationFiled: June 18, 2019Publication date: September 9, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Tetsuo GOCHO, Yuzo FUKUZAKI, Shinichi MIYAKE, Kazuyuki TOMIDA
-
Publication number: 20210233998Abstract: A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.Type: ApplicationFiled: August 13, 2019Publication date: July 29, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kazuyuki TOMIDA
-
Publication number: 20210225841Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.Type: ApplicationFiled: April 7, 2021Publication date: July 22, 2021Inventors: Hidetoshi OISHI, Koichi MATSUMOTO, Kazuyuki TOMIDA
-
Patent number: 11004851Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.Type: GrantFiled: June 4, 2020Date of Patent: May 11, 2021Assignee: SONY CORPORATIONInventors: Hidetoshi Oishi, Koichi Matsumoto, Kazuyuki Tomida
-
Publication number: 20210005714Abstract: To further reduce contact resistance when a current or a voltage is taken out from a metal layer. A conductive structure including: an insulating layer; a metal layer provided on one surface of the insulating layer to protrude in a thickness direction of the insulating layer; and a two-dimensional material layer provided along outer shapes of the metal layer and the insulating layer from a side surface of the metal layer to the one surface of the insulating layer.Type: ApplicationFiled: January 22, 2019Publication date: January 7, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kazuyuki TOMIDA
-
Publication number: 20200303376Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.Type: ApplicationFiled: June 4, 2020Publication date: September 24, 2020Applicant: SONY CORPORATIONInventors: Hidetoshi OISHI, Koichi MATSUMOTO, Kazuyuki TOMIDA