Abstract: Disclosed are a super-resolution imaging system (1, 41, 51), a super-resolution imaging method, a biological sample identification system (4, 61) and method, a nucleic acid sequencing imaging system (5) and method, and a nucleic acid identification system (6) and method. The super-resolution imaging system (1, 41, 51) includes an illumination system (A) and an imaging system (B). The illumination system (A) outputs excitation light to irradiate a biological sample to generate excited light, and the imaging system (B) collects and records the excited light to generate an excited light image. The illumination system (A) includes an excitation light source (10, 10a) and a structured light generation and modulation device (11, 11a). The excitation light source (10, 10a) outputs the excitation light, and the structured light generation and modulation device (11, 11a) modulates the excitation light into structured light to irradiate the biological sample to generate the excited light.

Abstract: An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.

Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

Abstract: Provided is a display backplate including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate.

Abstract: A physical layer retransmission control method is used for retransmission control of a transmission system. The transmission system includes a first transmission terminal, a second transmission terminal and a transmission channel. The first transmission terminal sends downlink data packets to the second transmission terminal through the transmission channel. The second transmission terminal sends retransmission control information to the first transmission terminal through the transmission channel. Each downlink data packet includes a sequence number and an abnormal state field. The sequence numbers in the consecutive downlink data packets are arranged in the order of transmission. The abnormal state field indicates the abnormal state of the data of the first transmission terminal.

Abstract: This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Abstract: A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of the memory cells in a first memory sub-block of a first memory block, determine verify loop counts of verify operations after programming the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming the memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as for the first memory sub-block of the first memory block, during the non-last pass program, not perform at least the verify operation corresponding to the last of the verify loop counts.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.

Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Abstract: A memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, a controller configured to control a read operation on the array of memory cells, and a row decoder coupled to the word lines and the controller and configured to, in the read operation, induce a coupling effect between a select word line and an adjacent unselect word line of the plurality of word lines, and discharge the select word line to a start read level due to at least the coupling effect.

Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.

Abstract: A memory device includes a first plurality of program lines of a first group, a second plurality of program lines of a second group, and a plurality of address lines. The second plurality of program lines are disposed next to and are parallel to the first plurality of program lines. The plurality of address lines are coupled to the first plurality of program lines and the second plurality of program lines respectively. The plurality of address lines are twisted and are intersected with the first plurality of program lines and the second plurality of program lines in a layout view. At least two adjacent program lines of the first plurality of program lines or the second plurality of program lines have lengths different from each other. A method is also disclosed herein.

Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.

Abstract: A memory device includes a first plurality of program lines of a first group, a second plurality of program lines of a second group, and a plurality of address lines. The second plurality of program lines are disposed next to and are parallel to the first plurality of program lines. The plurality of address lines are coupled to the first plurality of program lines and the second plurality of program lines respectively. The plurality of address lines are twisted and are intersected with the first plurality of program lines and the second plurality of program lines in a layout view. At least two adjacent program lines of the first plurality of program lines or the second plurality of program lines have lengths different from each other. A method is also disclosed herein.

Abstract: A method for programming a memory system including a plurality of memory cells includes performing a first program operation on the plurality of the memory cells. The method also includes identifying a first memory cell and a second set of memory cell from the plurality of memory cells based on threshold voltages of the plurality of memory cells after performing the first program operations. The method further includes performing a second operation on the plurality of the memory cells by applying a first cross voltage to the first memory cell and a second cross voltage to the second memory cell.

Abstract: A memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, a controller configured to control a read operation on the array of memory cells, and a row decoder coupled to the word lines and the controller and configured to, in the read operation, induce a coupling effect between a select word line and an adjacent unselect word line of the plurality of word lines, and discharge the select word line to a start read level due to at least the coupling effect.

Abstract: A sense circuit of a memory cell includes a first switch, a sense node, a third switch, a connection node, a fourth switch, and a memory cell coupled in series. A boost driver is coupled to the sense node. A second switch and the connection node are coupled in series. The boost driver outputs a first voltage when the first, second, third, fourth switches are turned on. The third switch is then turned off and the boost driver outputs a second voltage higher than the first voltage such that the voltage level at the sense node is not higher than a system voltage. The third switch is turned on, then turned off and the boost driver outputs an intermediate voltage between the first voltage and the second voltage. A state of the memory cell is determined during output of the intermediate voltage.

Abstract: A storage array includes multiple wordlines of storage cells that can be selectively charged to an erase voltage or an inhibit voltage. Control logic associated with the storage array can perform erase verify in stages. On a first erase verify pass, the control logic can set wordlines of an erase block or subblock to a first erase voltage. On a second erase verify pass, the control logic can trigger a second erase verify pulse and set passing wordlines to an inhibit voltage, and failing wordlines to a second erase voltage higher than the first voltage. Inhibiting the already passing wordlines can reduce threshold voltage differences among the wordlines.

Abstract: A memory device includes N rows of memory cells and N word lines coupled thereto, respectively. A method of reading data from the memory device includes: applying a first pre-pulse voltage to an nth word line while applying a second pre-pulse voltage to an adjacent word line adjacent to the nth word line, the second pre-pulse voltage exceeding the first pre-pulse voltage, and n being an integer ranging from 1 to N; grounding the nth word line while maintaining the second pre-pulse voltage on the adjacent word line; pulling a voltage on the nth word line towards a start read level; and prior to the voltage on the nth word line reaching the start read level, driving a voltage on the adjacent word line to the first pre-pulse voltage.