Abstract: A memory device includes a peripheral circuit and a memory array coupled with the peripheral circuit. The memory array includes at least one memory block. The peripheral circuit includes at least one row decoder. One memory block is correspondingly connected with one row decoder. The row decoder includes a logic circuit and a level conversion circuit. The logic circuit is configured to generate a first control signal, a second control signal, and a first output signal based on an address signal and a status signal of the memory block correspondingly connected with the row decoder. A level of the second control signal is higher than a level of the first control signal. The level conversion circuit is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal respectively.

Abstract: A display method for a virtual keyboard and an electronic device and a storage medium are provided. The display method includes: displaying the virtual keyboard on an interface; determining, in response to a split operation for the virtual keyboard, a region where virtual keys of a first part of the virtual keyboard are located as a first key region, and a region where virtual keys of a second part of the virtual keyboard are located as a second key region; and adjusting the first key region and the second key region and displaying a functional region between the first key region and the second key region.

Abstract: The present disclosure discloses a memory device, a memory system, and a method for operating a memory device, belonging to the field of storage technology. In the present disclosure, by turning off the first switch circuit, turning on the second switch circuit and providing the first voltage to the first node, the first voltage is applied on the second terminal of the drive transistor through the second switch circuit and the source line, the second terminal of the drive transistor is coupled to a control terminal, such that the voltage of the control terminal changes as the voltage of the second terminal changes, since the first voltage is greater than the threshold voltage of the drive transistor, the drive transistor is turned on to trigger the drive transistor to assist the corresponding memory string in performing a gate-induced-drain-leakage (GIDL) erase.

Abstract: A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a first memory cell and a second memory cell coupled to a same bit line and being adjacent. The peripheral circuit includes a page buffer circuit. The page buffer circuit includes: a sensing node coupled to the bit line; a first latch circuit coupled to the sensing node, and configured to latch a programmed state of first memory cell; a charge and discharge circuit coupled to the sensing node, and configured to: charge the sensing node, and discharge the sensing node, wherein discharge duration of the sensing node is related to the programmed state; and a second latch circuit coupled to the sensing node, and configured to latch, according to a voltage value of the sensing node after the discharge duration, information of whether second memory cell passes program verification.

Abstract: Examples of the present disclosure disclose a memory and an operation method thereof, a memory system and an electronic device. The memory includes a memory cell array and a page buffer, wherein the page buffer is disposed correspondingly to a bit line of the memory cell array and includes: latches which are coupled to the bit line through a sense node of the page buffer; and at least one common data transmission circuit, wherein a first port of the common data transmission circuit is coupled with the sense node and a second port of the common data transmission circuit is coupled with at least two of the latches, wherein the at least two of the latches are configured for data sensing through the common data transmission circuit respectively.

Abstract: A touch display substrate and a touch display apparatus are provided. The touch display substrate including: a display region and a non-display region, the display region including a first display region and a second display region, the first display region surrounding at least one side of the second display region; the touch display substrate includes a base substrate and a display structure layer and a touch structure layer disposed on the base substrate sequentially; the first display region includes a first touch assembly, and the second display region includes a second touch assembly; the display structure layer includes multiple pixel circuits located in the first display region and multiple light emitting elements located in the first display region and second display region; the first touch assembly is located in the touch structure layer, and the second touch assembly is located in the display structure layer and/or the touch structure layer.

Abstract: A memory device includes a memory array and a control logic coupled to the memory array. The memory array includes memory blocks. Each memory block includes memory cell strings, and each memory cell string includes a first memory cell, second memory cells, and a third memory cell. The second memory cells are between the first memory cell and the third memory cell. The first memory cell is coupled to a bit line, the third memory cell is coupled to a source line, the first memory cell is coupled with a first dummy word line, the second memory cells are respectively coupled with second word lines, and the third memory cell is coupled with a third word line.

Abstract: A video transmission system includes a first transmission terminal, a second transmission terminal and a transmission channel. The first transmission terminal includes a transmission memory, and stores a retransmittable data packet into the transmission memory and sends the retransmittable data packet to the second transmission terminal. The second transmission terminal judges the abnormal state of the received retransmittable data packet, generates and sends retransmission control information according to a judgment result. The first transmission terminal retransmits the retransmittable data packet to the second transmission terminal according to the retransmission control information. The first transmission terminal sends a real-time data packet to the second transmission terminal. The real-time data packet is used to transmit video timing control signals.

Abstract: Example memory devices, memory systems, and methods for reducing program disturb in NAND flash memory are disclosed. One example method includes applying, at a first time, a first voltage to a first select line coupled to a first select gate transistor, where the memory device includes a memory cell array. The memory cell array includes a memory string. The memory string includes the first select gate transistor, multiple memory cells, and a source select gate transistor. The multiple memory cells are positioned between the first select gate transistor and the source select gate transistor. The source select gate transistor is coupled to a source line of the memory cell array. A second voltage is applied at a second time to the first select line, where the second time is after the first time, and the second voltage is larger than the first voltage.

Abstract: According to some aspects, a memory includes a bit line discharge circuit and a bit line coupled to the bit line discharge circuit. The bit line discharge circuit includes a transistor, a control branch, and a first discharge branch. A gate of the transistor is connected with the control branch. One of a source or a drain of the transistor is connected with the first discharge branch. Another of the source or the drain of the transistor is connected with the bit line. The control branch is configured to turn on the transistor. The first discharge branch is configured to discharge the bit line at a set discharge speed when the transistor is turned on.

Abstract: This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

Abstract: Devices, systems, and methods for counting a quantity of fail-bits in a memory device using a VFC circuit are disclosed. The VFC circuit can be calibrated via an offset adjustment mechanism to compensate an internal mismatch. The VFC circuit can include a processing unit and a circuit coupled to the processing unit. The processing unit can receive a first signal representing a number of detected fail-bits in the memory array, process the first signal and an offset signal, and generate a second signal representing a quantity of fail-bits. The circuit can receive the first and second signals, determine a difference between the quantity of fail-bits represented by the second signal and the number of detected fail-bits represented by the first signal, adjust the offset signal according to the difference, and provide the offset signal to the processing unit.

Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

Abstract: A physical layer retransmission control method is used for retransmission control of a transmission system. The transmission system includes a first transmission terminal, a second transmission terminal and a transmission channel. The first transmission terminal sends downlink data packets to the second transmission terminal through the transmission channel. The second transmission terminal sends retransmission control information to the first transmission terminal through the transmission channel. Each downlink data packet includes a sequence number and an abnormal state field. The sequence numbers in the consecutive downlink data packets are arranged in the order of transmission. The abnormal state field indicates the abnormal state of the data of the first transmission terminal.

Abstract: This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Abstract: A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of the memory cells in a first memory sub-block of a first memory block, determine verify loop counts of verify operations after programming the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming the memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as for the first memory sub-block of the first memory block, during the non-last pass program, not perform at least the verify operation corresponding to the last of the verify loop counts.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.

Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Abstract: A memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, a controller configured to control a read operation on the array of memory cells, and a row decoder coupled to the word lines and the controller and configured to, in the read operation, induce a coupling effect between a select word line and an adjacent unselect word line of the plurality of word lines, and discharge the select word line to a start read level due to at least the coupling effect.