Abstract: A storage array includes multiple wordlines of storage cells that can be selectively charged to an erase voltage or an inhibit voltage. Control logic associated with the storage array can perform erase verify in stages. On a first erase verify pass, the control logic can set wordlines of an erase block or subblock to a first erase voltage. On a second erase verify pass, the control logic can trigger a second erase verify pulse and set passing wordlines to an inhibit voltage, and failing wordlines to a second erase voltage higher than the first voltage. Inhibiting the already passing wordlines can reduce threshold voltage differences among the wordlines.

Abstract: A memory device includes N rows of memory cells and N word lines coupled thereto, respectively. A method of reading data from the memory device includes: applying a first pre-pulse voltage to an nth word line while applying a second pre-pulse voltage to an adjacent word line adjacent to the nth word line, the second pre-pulse voltage exceeding the first pre-pulse voltage, and n being an integer ranging from 1 to N; grounding the nth word line while maintaining the second pre-pulse voltage on the adjacent word line; pulling a voltage on the nth word line towards a start read level; and prior to the voltage on the nth word line reaching the start read level, driving a voltage on the adjacent word line to the first pre-pulse voltage.

Abstract: A sense circuit of a memory cell includes a first switch, a sense node, a third switch, a connection node, a fourth switch, and a memory cell coupled in series. A boost driver is coupled to the sense node. A second switch and the connection node are coupled in series. The boost driver outputs a first voltage when the first, second, third, fourth switches are turned on. The third switch is then turned off and the boost driver outputs a second voltage higher than the first voltage such that the voltage level at the sense node is not higher than a system voltage. The third switch is turned on, then turned off and the boost driver outputs an intermediate voltage between the first voltage and the second voltage. A state of the memory cell is determined during output of the intermediate voltage.

Abstract: A memory device includes N rows of memory cells and N word lines coupled thereto, respectively. A method of reading data from the memory device includes: applying a first pre-pulse voltage to an nth word line while applying a second pre-pulse voltage to an adjacent word line adjacent to the nth word line, the second pre-pulse voltage exceeding the first pre-pulse voltage, and n being an integer ranging from 1 to N; grounding the nth word line while maintaining the second pre-pulse voltage on the adjacent word line; pulling a voltage on the nth word line towards a start read level; and prior to the voltage on the nth word line reaching the start read level, driving a voltage on the adjacent word line to the first pre-pulse voltage.

Abstract: A method for programming a memory system including a plurality of memory cells includes performing a first program operation on the plurality of the memory cells. The method also includes identifying a first memory cell and a second set of memory cell from the plurality of memory cells based on threshold voltages of the plurality of memory cells after performing the first program operations. The method further includes performing a second operation on the plurality of the memory cells by applying a first cross voltage to the first memory cell and a second cross voltage to the second memory cell.

Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.

Abstract: A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.

Abstract: Methods include incrementing a first read count in response to performing a read operation on a memory cell of a block of memory cells, the first read count corresponding to a first portion of memory cells of the block of memory cells; incrementing a second read count in response to performing the read operation on the memory cell of the block of memory cells, the second read count corresponding to a second portion of memory cells of the block of memory cells; resetting the first read count in response to performing an erase operation on the first portion of memory cells of the block of memory cells; and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.

Abstract: Methods include incrementing a first read count in response to performing a read operation on a memory cell of a block of memory cells, the first read count corresponding to a first portion of memory cells of the block of memory cells; incrementing a second read count in response to performing the read operation on the memory cell of the block of memory cells, the second read count corresponding to a second portion of memory cells of the block of memory cells; resetting the first read count in response to performing an erase operation on the first portion of memory cells of the block of memory cells; and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: Described is a new process for applying a metal coating to a non-conductive substrate comprising the steps of (a) contacting the substrate with an activator comprising a noble metal/group IVA metal sol to obtain a treated substrate, (b) contacting said treated substrate with a composition comprising a solution of: (i) a Cu(II), Ag, Au or Ni soluble metal salt or mixtures thereof, (ii) 0.05 to 5 mol/l of a group IA metal hydroxide and (iii) a complexing agent for an ion of the metal of said metal salt comprising an organic material having a cumulative formation constant log K of from about 0.73 to about 21.95 for an ion of the metal of said metal salt, characterised in that the composition according to step (b) is treated with an electrical current for a period of time prior to and/or during contacting said solution with the substrate.

Abstract: The invention relates to a gate driving device for Thin Film Transistor liquid crystal display comprising: a plurality of shift registers directly deposited on an array substrate, said shift registers being composed of effect transistors and a capacitor, obtaining a gate driving signal voltage by controlling an input signal. Said shift register can be realized by 5-layer mask process or 4-layer mask process, by arranging the field effect transistors on the margin part outside the active region on the substrate or at the edge of the substrate, and then directly depositing them on an array substrate. The invention obtains a gate driving signal voltage by the shift registers directly deposited on the substrate, thus overcoming the shortage of the need of driving chips and film layers in the prior art, substantially reducing the production cost for LCD.

Abstract: A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source and drain electrodes overlap a source region and a drain region of the active layer, respectively, and a thin film of SiNx or SiOxNy through which electrons are allowed to tunnel is provided between the active layer and the source and drain electrodes.

Abstract: The invention relates to a gate driving device for Thin Film Transistor liquid crystal display comprising: a plurality of shift registers directly deposited on an array substrate, said shift registers being composed of effect transistors and a capacitor, obtaining a gate driving signal voltage by controlling an input signal. Said shift register can be realized by 5-layer mask process or 4-layer mask process, by arranging the field effect transistors on the margin part outside the active region on the substrate or at the edge of the substrate, and then directly depositing them on an array substrate. The invention obtains a gate driving signal voltage by the shift registers directly deposited on the substrate, thus overcoming the shortage of the need of driving chips and film layers in the prior art, substantially reducing the production cost for LCD.

Abstract: A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source and drain electrodes overlap a source region and a drain region of the active layer, respectively, and a thin film of SiNx or SiOxNy through which electrons are allowed to tunnel is provided between the active layer and the source and drain electrodes.

Abstract: Provided are a target material for manufacturing an electrode film of a semiconductor device, methods of manufacturing the target material and manufacturing the electrode film. The target material comprises Al-RE alloy or Al—Ni-RE alloy, in which RE is a mixture of rare earth elements comprising La, Ce, Pr, and Nd.