Abstract: For assembling a heat pump, an apparatus includes a loading part located in an initial section of the fully automatic intelligent production line of an integrated thermal management module. The apparatus includes a first assembling part, located downstream of the loading part, that assembles a refrigerant side components of the heat pump. The apparatus includes a first testing part, located downstream of the first assembly part, that tests the refrigerant side components. The apparatus includes a second assembling part, located downstream of the loading part, that assembles the cooling water side components of the heat pump. The apparatus includes a second testing part, located downstream of the second assembling part, that tests the cooling water side components. The apparatus includes a finished product part, located downstream of the second testing part, that outputs a finished product.

Abstract: An electric field generating device includes n electrodes, an electrical signal generator and a control signal generator. The control signal generator is electrically connected to the electrical signal generator, and configured to control the electrical signal generator to apply a first electrical signal to m electrodes of the n electrodes, and apply a second electrical signal to at least two electrodes of n-m electrodes, to generate an electric field between the electrodes with the first electrical signal and the electrodes with the second electrical signal; where n is an integer not less than 3, 1?m<n, m is an integer, and a voltage of the second electrical signal is less than a voltage of the first electrical signal.

Abstract: A 9B/10B encoding method is used for encoding a 9-bit source sequence set, including first type, second type and third type of 9-bit source sequence sets, into a 10-bit target sequence set. The first type of 9-bit source sequence set only includes 9-bit source sequences with difference values of 1 and ?1. After inserting 1-bit data “0” or “1” in each sequence, each sequence is encoded as a 10-bit target balanced sequence; the second type of 9-bit source sequence set alternatively includes only 9-bit source sequences with difference values of 3 or ?3. After inserting 1-bit data “0” or “1” into each sequence, each sequence is encoded into a pair of 10-bit target unbalanced sequences with a difference value of ±2; each sequence in the third type of 9-bit source sequence set is encoded as a pair of 10-bit target unbalanced sequences that are opposite numbers for each other.

Abstract: Compounds having methyltransferase inhibitory activity are disclosed. The compounds have the structures The compounds disclosed are useful in the treatment of cancer and similar diseases associated with inappropriate methyltransferase activity.

Abstract: A wall mountable sensor module includes a housing defining an internal space that is segmented into a first internal space and a second internal space. The first internal space defines an air channel that extends from an air inlet to an air outlet. Two or more sensors are configured to be exposed to the air flow channel. A first sensor is configured to detect a first air parameter and a second sensor is configured to detect a second different air parameter, wherein the second sensor is situated downstream of the first sensor in the air flow channel. The sensor module includes a fan housed by the housing, the fan configured to cause an airflow to flow in through the air inlet, through the air flow channel thereby exposing each of the sensors to the airflow, and out through the air outlet.

Abstract: A method of video decoding includes that: a decoder inputs a feature bitstream of a current picture into a decoding network and obtains first feature information outputted by an i-th middle layer of the decoding network, wherein i is a positive integer; and the decoder inputs the first feature information into a j-th middle layer of a task analysis network and obtains a task analysis result outputted by the task analysis network, wherein j is a positive integer. Provided are also a method for video encoding and a video decoder.

Abstract: A heterojunction cell and a method for preparing same. The heterojunction cell comprises: a semiconductor substrate layer; and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on the surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises: a bottom intrinsic layer; and a wide-band-gap intrinsic layer, which is located on the surface of the side of the bottom intrinsic layer that is away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer being greater than the band gap of the bottom intrinsic layer. The band gap of a wide-band-gap intrinsic layer is larger, and when sunlight irradiates a heterojunction cell, photons, the energy of which is less than that of the band gap of the wide-band-gap intrinsic layer, cannot be subjected to parasitic absorption.

Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) includes a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.

Abstract: The display drive circuit includes: an interface circuit for acquiring a plurality of grayscale data and a plurality of current gain data; a command processing circuit electrically coupled with the interface circuit; a cache circuit electrically coupled with the interface circuit and configured for caching the plurality of grayscale data and the plurality of current gain data; a current source circuit electrically coupled with the command processing circuit and including a plurality of channel current sources; a channel grayscale control circuit, electrically coupled with the command processing circuit, the cache circuit and the current source circuit, and configured for respectively controlling duration of turning on of the plurality of channel current sources according to the plurality of grayscale data; and a channel current control circuit electrically coupled with the cache circuit and the current source circuit, and configured for respectively controlling output currents of the plurality of channel curr

Abstract: A proactive fault-tolerant scheme which improves performance and energy efficiency for NoCs. The fault-tolerant scheme allows routers to switch among several different fault-tolerant operations. Each operation mode has different trade-offs among fault-tolerant capability, retransmission traffic, latency, and energy efficiency. Another example provides a proactive, dynamic control policy to balance and optimize the dynamic interactions and trade-offs. The example control policy uses example machine learning algorithm called reinforcement learning (RL). The example RL-based controller independently observes a set of NoC system parameters at runtime, and over time they evolve optimal per-router control policies. By automatically and optimally switching among the four fault-tolerant modes, the trained control policy results in minimizing system level network latency and maximizing energy efficiency while detecting and correcting errors.

Abstract: An embodiment generates an initial set of training data from monitoring data. The initial set of training data is generated by combining outputs from a plurality of pretrained classifiers. The embodiment trains a new classification model using the initial set of training data to identify anomalies in monitoring data. The embodiment performs a multiple-level clustering of the data samples resulting in a plurality of clusters of sub-clusters of data samples, and generates a review list of data samples by selecting a representative data sample from each of the clusters. The embodiment receives an updated data sample from the expert review that includes a revised target classification for at least one of the data samples of the expert review list. The embodiment then trains another replacement classification model using a revised set of training data that includes the updated data sample and associated revised target classification.

Abstract: A near-eye display apparatus is disclosed. The near-eye display apparatus includes a lens and an optical path folding assembly. The lens is configured to receive incident light of a first image, which is projected by a micro-display, and shape the first image; the lens includes a primary optical axis and a first lens face and a second lens face which are opposed in a first direction where the primary optical axis of the lens is positioned, a curvature radius of the first lens face is within a range of 70 to 100 millimeters, and a curvature radius of the second lens face is within a range of 10 to 30 millimeters; and the optical path folding assembly is configured to receive light of the first image shaped by the lens and fold an optical path from the lens to an exit pupil of the near-eye display apparatus.

Abstract: A light emitting baseplate and a method of manufacturing the same, and a display device. The light emitting baseplate includes a substrate, and a plurality of light emitting units and a plurality of supporting columns located on the substrate. The plurality of supporting columns are located on surfaces of the light emitting units away from the substrate. A surface of each of the light emitting units away from the substrate is provided with the supporting columns respectively. Heights of the supporting columns are equal. The supporting columns disposed on a surface of a same light emitting unit are symmetrically distributed about a symmetrical axis of the surface. The display device includes the light emitting baseplate.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a preparation method. The preparation method of the memory comprises the following steps: firstly forming a basic structure body; secondly, slotting the basic structure body; thirdly, forming a preset number of memory cell holes in the a segmentation groove, an insulating medium being arranged between every two adjacent memory cell holes, a vertical electrode being arranged in the memory cell hole, and a memory medium layer being arranged between the vertical electrode and an interdigital structure; and in the third step, before the memory medium is arranged, the preparation method comprises the following steps: performing doping diffusion on the first conducting medium located on the inner wall of the segmentation groove, so that the first conducting medium close to the inner wall of the segmentation groove forms a buffer area made of a low-doped semiconductor material.

Abstract: The present disclosure relates to a diisocyanate stabilizer, use of the diisocyanate stabilizer for stabilizing diisocyanate, and a diisocyanate composition comprising the stabilizer. The diisocyanate stabilizer comprises a sterically hindered phenol other than butylated hydroxytoluene, a thioether, and a phosphite other than triphenyl phosphite. The present disclosure aims to provide a diisocyanate stabilizer which can make diisocyanates maintain stable during long-term storage and heating condition.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a fabrication method, and relates to the preparation technology of memories. The memory comprises an underlying circuit part and a basic structure body disposed above the underlying circuit part, wherein the basic structure body is divided into two independent interdigitated structures by a curve-shaped division groove, at least three memory cell holes are formed in the curve-shaped division groove side by side, a vertical electrode is disposed in each memory cell hole, and the memory medium is an insulating medium; and a buffer region is placed on the inner wall of the memory cell hole and at the position of a first conducting medium layer, the buffer region protrudes from the inner wall of the memory cell hole to the central axis of the memory cell hole, and the buffer region is connected to the memory medium.

Abstract: A graphene anti-corrosion coating is described that comprises an epoxy resin and graphene subjected to surface modification, where the addition amount of the graphene is 0.01-0.2 wt % of the total mass of coating solid. By performing surface treatment on the graphene, the dispersity of the graphene in the coating is improved, and the compactness of the coating is enhanced.

Abstract: The present invention belongs to the technical field of water treatment, and in particular to a magnetic powder strengthened method for removing nitrate nitrogen and inorganic phosphorus, which includes the following steps: (1) mixing permanent magnetic material powder with paramagnetic Fe3O4 powder, and magnetizing the mixture in a magnetic field to prepare magnetic powder; (2) adding the magnetic powder directly or in a form of granular filler into a water treatment reaction vessel; and (3) allowing the to-be-treated water to enter the water treatment reaction vessel, performing a chemical reaction of removing nitrate nitrogen and inorganic phosphorus in the presence of a reducing agent, and discharging the water after the reaction is completed. By adopting the method of the present invention, a uniform and fine magnetic field can be provided, thus the reaction efficiency is improved, and the process is simplified and the cost is lowered.

Abstract: A method is described for seismic inversion with uncertainty quantification including performing low frequency Markov Chain Monte Carlo (MCMC) processes on rock physics models to generate low frequency models (LFMs) of rock properties and training a deep neural network using the low frequency models and synthetic seismograms to generate a trained neural network. Given a seismic dataset, the trained neural network can generate a high frequency rock property model and then broad-band MCMC processes can be performed on the high frequency rock property model for uncertainty quantification. The method is executed by a computer system.