Abstract: An interconnect structure is disposed over a semiconductor substrate. The interconnect structure includes a plurality of interconnect layers. A first thin-film transistor (TFT) and a second TFT are disposed over the semiconductor substrate. The first TFT and the second TFT each vertically extend through at least a subset of the interconnect layers. An opening is formed in the interconnect structure. The opening is disposed between the first TFT and the second TFT. A sensing film is disposed over a bottom surface and side surfaces of the opening.

Abstract: A semiconductor structure includes an isolation structure penetrating through a semiconductor substrate, a biosensor coupled to the semiconductor substrate, and a cover. The biosensor includes a bio-sensing device, a voltage-reference device spaced apart from the bio-sensing device, thermal management devices in proximity to the bio-sensing device, and a patterned dielectric layer. Each of the bio-sensing and voltage-reference devices includes a gate structure disposed on a bottom surface of the semiconductor substrate, source/drain (S/D) regions disposed in the semiconductor substrate, and a portion of a sensing film disposed on the semiconductor substrate and capacitively coupled to the gate structure and the S/D regions. Each thermal management devices includes a gate structure underlying the isolation structure or the semiconductor substrate. The patterned dielectric layer overlying the semiconductor substrate includes sensing wells located above the voltage-reference and bio-sensing devices.

Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.

Abstract: A semiconductor device includes a substrate, an interconnect, and a sensor. The substrate includes devices therein and has a front side and a rear side opposite to the front side. The interconnect is disposed on the front side and electrically coupled to the devices. The sensor is disposed over the substrate and in the interconnect, and includes a sensing element and a reference element. The sensing element is disposed in a topmost layer of the interconnect and exposed therefrom, where the sensing element is electrically coupled to a first device of the devices through the interconnect. The reference element is disposed in the topmost layer of the interconnect and exposed therefrom, where the reference element is laterally spaced from the sensing element and is electrically coupled to a second device of the devices through the interconnect.

Abstract: A semiconductor device includes a substrate, an interconnect, and a sensor. The substrate includes devices therein and has a front side and a rear side opposite to the front side. The interconnect is disposed on the front side and electrically coupled to the devices. The sensor is disposed over the substrate and in the interconnect, and includes a sensing element and a reference element. The sensing element is disposed in a topmost layer of the interconnect and exposed therefrom, where the sensing element is electrically coupled to a first device of the devices through the interconnect. The reference element is disposed in the topmost layer of the interconnect and exposed therefrom, where the reference element is laterally spaced from the sensing element and is electrically coupled to a second device of the devices through the interconnect.

Abstract: A semiconductor structure includes a sensor and a dielectric layer. The sensor includes a first device and a second device, the first device includes a first field effect transistor (FET) and a first sensing portion of a sensing film coupled to the first FET, the second device includes a second FET and a second sensing portion of the sensing film coupled to the second FET, where the first device and the second device have different functions, and the second sensing portion is flatter than the first sensing portion. The dielectric layer is disposed on the sensing film and includes a sensing well located above the first device and the second device.

Abstract: A substrate has a first side and a second side vertically opposite to the first side. A sensing transistor is disposed at least in part over the first side of the substrate. A plurality of voltage reference transistors is disposed at least in part over the first side of the substrate. The voltage reference transistors are disposed on different lateral sides of the sensing transistor. A structure is disposed over the second side of the substrate. The structure defines one or more openings configured to collect a fluid. A sensing film is disposed over the second side of the substrate, wherein the sensing transistor is configured to detect, at least in part through capacitive coupling, a presence of one or more predefined miniature targets in the fluid that attach to the sensing film in the opening that is vertically aligned with the sensing transistor.

Abstract: A semiconductor structure includes a sensor, a patterned dielectric layer, and a cover disposed on the patterned dielectric layer. The sensor includes a bio-sensing device and at least one voltage-reference device disposed in proximity to the bio-sensing device. The bio-sensing device includes a first field effect transistor (FET) and a first sensing portion of a sensing film capacitively coupled to the first FET, and the first sensing portion is concave toward the first FET. The at least one voltage-reference device includes a second FET and a second sensing portion of the sensing film capacitively coupled to the second FET. The patterned dielectric layer is disposed on the sensing film and includes at least one sensing well located above the at least one voltage-reference device and the bio-sensing device. The cover includes fluid channels communicating with the at least one sensing wells.

Abstract: An interconnect structure is disposed over a semiconductor substrate. The interconnect structure includes a plurality of interconnect layers. A first thin-film transistor (TFT) and a second TFT disposed over the semiconductor substrate. The first TFT and the second TFT each vertically extend through at least a subset of the interconnect layers. An opening is formed in the interconnect structure. The opening is disposed between the first TFT and the second TFT. A sensing film is disposed over a bottom surface and side surfaces of the opening.

Abstract: A substrate has a first side and a second side vertically opposite to the first side. A sensing transistor is disposed at least in part over the first side of the substrate. A plurality of voltage reference transistors is disposed at least in part over the first side of the substrate. The voltage reference transistors are disposed on different lateral sides of the sensing transistor. A structure is disposed over the second side of the substrate. The structure defines one or more openings configured to collect a fluid. A sensing film is disposed over the second side of the substrate, wherein the sensing transistor is configured to detect, at least in part through capacitive coupling, a presence of one or more predefined miniature targets in the fluid that attach to the sensing film in the opening that is vertically aligned with the sensing transistor.

Abstract: A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film. The substrate includes devices disposed therein. The interconnect is disposed on the substrate and electrically coupled to the devices, where the interconnect includes a plurality of build-up layers and a through hole formed therein. The first transistor is disposed in the interconnect and vertically extends through at least one of the plurality of build-up layers, and the first transistor is electrically coupled to a first device of the devices through the interconnect. The second transistor is disposed in the interconnect and vertically extends through the at least one of the plurality of build-up layers, and the second transistor is electrically coupled to a second device of the devices through the interconnect, where the first transistor and the second transistor are laterally separated from one another through the through hole.

Abstract: A substrate has a first side and a second side opposite the first side. A first transistor has a first gate, a second transistor has a second gate, and a third transistor has a third gate. The first gate, the second gate, and the third gate are each disposed over the first side of the substrate. The second gate is disposed between the first gate and the third gate. The first gate and the third gate have different material compositions. A structure is disposed over the second side of the substrate. The structure includes a first opening aligned with the first transistor, a second opening aligned with the second transistor, and a third opening aligned with the third transistor. A sensing film is disposed over the second side of the substrate. The sensing film is configured to attach to one or more predefined miniature targets.

Abstract: A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film. The substrate includes devices disposed therein. The interconnect is disposed on the substrate and electrically coupled to the devices, where the interconnect includes a plurality of build-up layers and a through hole formed therein. The first transistor is disposed in the interconnect and vertically extends through at least one of the plurality of build-up layers, and the first transistor is electrically coupled to a first device of the devices through the interconnect. The second transistor is disposed in the interconnect and vertically extends through the at least one of the plurality of build-up layers, and the second transistor is electrically coupled to a second device of the devices through the interconnect, where the first transistor and the second transistor are laterally separated from one another through the through hole.

Abstract: An IC device design system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs, the storage medium and the code being configured to, with the processor, cause the system to receive an IC device layout diagram including a gate region having a width extending at least from a first edge of an active region to a second edge of the active region and a gate via at a location within the active region and along the width, receive a first gate resistance value corresponding to the gate region, retrieve a second gate resistance value from a resistance value reference based on the location and the width, and based on the second gate resistance value being greater than the first gate resistance value, add a gate terminal node and a resistor to a netlist corresponding to the gate region.

Abstract: A biosensor including a first sensor, a second sensor, a patterned dielectric layer and a cover is provided. The first sensor includes a first voltage-reference device and a first bio-sensing device. The second sensor is disposed adjacent to the first sensor, the second sensor includes a second voltage-reference device and a second bio-sensing device, the first sensor is spaced apart from the second sensor by a lateral distance, and the lateral distance is greater than a half of an average lateral dimension of the first voltage-reference device and the second voltage-reference device. The patterned dielectric layer includes sensing wells located above the first voltage-reference device, the first bio-sensing device, the second voltage-reference device and the second bio-sensing device. The cover includes fluid channels communicating with the sensing wells.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second active region edges, calculating a gate resistance value based on the location and first and second active region edges, based on the resistance value, modifying the IC layout diagram by changing the location of the gate via along the gate region and/or adding another gate via positioned at another location along the gate region, and storing the modified IC layout diagram in a storage device.

Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.

Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.