Abstract: The present invention discloses a multi-source data fusion method and system for dynamic system scenario behavior deduction and reliability prediction analysis, a computer device, and a storage medium. Based on a Markov/CCMT dynamic reliability prediction analysis method and combined with a multi-source data fusion and assimilation method, the method simulates and statistically analyzes complex dynamic behavior characteristics of digital process control with strong interactive coupling, nonlinearity and high uncertainty by Monte Carlo probability model random sampling, and then achieves forward deduction analysis and reliability prediction of a system operation state through dynamic search analysis of a system state transition probability matrix model.

Abstract: The fiber optic connector includes a connector head module, a mounting seat, a rear boot, an engaging module and a sheath member. The mounting seat is mounted to a rear end of the connector head module, and includes an external threaded portion. The rear boot is connected to a rear end of the mounting seat. The engaging module is removably coupled to the connector head module. The sheath member includes an internal threaded portion that is formed in an inner surface of the sheath member. When the engaging module is removed from the connector head module, the sheath member can be attachable to the mounting seat with the external threaded portion being threadedly engaged with the external threaded portion of the mounting seat.

Abstract: An optical fiber connector includes a connecting unit, an adapter unit, and an attenuation unit. The adapter unit includes an insertion seat connected removably to a main housing of the connecting unit, and two guide frame bodies located respectively at two opposite sides of the insertion seat in a transverse direction. The insertion seat has two insertion holes spaced apart in the transverse direction and extending in a front-rear direction. Each guide frame body extends in the front-rear direction away from the connecting unit. The attenuation unit includes two attenuation components, two rear ferrules, and two front ferrules. The attenuation components are arranged in the transverse direction and disposed within the main housing. The rear ferrules respectively extend rearwardly from rear ends of the attenuation components into the insertion holes. The front ferrules respectively extend forwardly from front ends of the attenuation components through and outwardly of the main housing.

Abstract: A protector installation device for an electronic device includes a shell and a protector. The shell is provided with an accommodating space, a first mounting end face, and a second mounting end face. The accommodating space is communicated to the second mounting end face of the shell from the first mounting end face of the shell, so that the accommodating space forms a placement opening in the first mounting end face, and the accommodating space forms a mounting opening in the second mounting end face. The placement opening is used for allowing the electronic device to be put into the accommodating space. The protector is arranged on the second mounting end face; and the protector blocks the mounting opening, so that the protector is fitted to a screen of the electronic device in the accommodating space via the mounting opening.

Abstract: The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

Abstract: A fiber optic adaptor includes a main shell body and an outer cover. The main shell body has a first end portion and a second end portion. The first end portion defines a first opening and is formed with two engaging grooves. The outer cover is removably disposed on and covering the first end portion, and has a cover body portion, two locking clips, and an identifier portion. The two locking clips protrudes from the cover and respectively engage the engaging grooves. The identifier portion is disposed on the cover body portion. The locking clips are operable to be removed respectively from the engaging grooves. The cover body portion defines a port outer opening, and a port key portion.

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Abstract: The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i?1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Abstract: The fiber optic connector includes a connector head module, a mounting seat, a rear boot, an engaging module and a sheath member. The mounting seat is mounted to a rear end of the connector head module, and includes an external threaded portion. The rear boot is connected to a rear end of the mounting seat. The engaging module is removably coupled to the connector head module. The sheath member includes an internal threaded portion that is formed in an inner surface of the sheath member. When the engaging module is removed from the connector head module, the sheath member can be attachable to the mounting seat with the external threaded portion being threadedly engaged with the external threaded portion of the mounting seat.

Abstract: This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Abstract: A fiber optic adaptor includes a main shell body and an outer cover. The main shell body has a first end portion and a second end portion. The first end portion defines a first opening and is formed with two engaging grooves. The outer cover is removably disposed on and covering the first end portion, and has a cover body portion, two locking clips, and an identifier portion. The two locking clips protrudes from the cover and respectively engage the engaging grooves. The identifier portion is disposed on the cover body portion. The locking clips are operable to be removed respectively from the engaging grooves. The cover body portion defines a port outer opening, and a port key portion.

Abstract: This disclosure relates to a device performing hash algorithm. A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation stage. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.

Abstract: The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i?1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Abstract: A fiber optic adapter includes a surrounding wall defining a communication space, two first protruding walls located in the communication space and connected to the surrounding wall, two second protruding walls located in the communication space and connected to the surrounding wall, and an error-proofing protrusion disposed on the surrounding wall, and located in a first key groove between the first protruding walls.

Abstract: This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Abstract: This disclosure relates to a device performing hash algorithm A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Abstract: A fiber optic adapter includes a surrounding wall defining a communication space, two first protruding walls located in the communication space and connected to the surrounding wall, two second protruding walls located in the communication space and connected to the surrounding wall, and an error-proofing protrusion disposed on the surrounding wall, and located in a first key groove between the first protruding walls.

Abstract: Generating a wizard includes receiving a scheme as an input source to form a received scheme, wherein the received scheme is a taxonomy, receiving a defined set of content files to form received content files, and loading the received content files and the received scheme. The received content files can be tagged using the received scheme. A wizard can be generated using the received scheme. The generated wizard is capable of use with an application utilizing the scheme, wherein a change in the received scheme is directly represented in the generated wizard.

Abstract: A computer-implemented method for remotely providing fonts for an electronic document comprises receiving a request to access an electronic document from a user terminal; locating an original version of the electronic document; selecting a code point encoding scheme from a plurality of code point encoding schemes based on a parameter in the request to access the electronic document; converting the original version of the electronic document to a second version of the electronic document based on the selected code point encoding scheme; and providing the second version of the electronic document to the user terminal.