Abstract: A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract: Among other things, one or more systems and techniques for width bias adjustment for a design layout are provided. During fabrication, characteristics of a component can change, such as size, width, position, etc., from how a design layout represents such components. Accordingly, a width bias table is used to identify a width bias value that can be applied between a first polygon and a second polygon to compensate for a characteristic change associated with at least one of the first polygon and the second polygon during fabrication. The width bias value is used during RC extraction to determine an electrical characteristic adjustment, such as an additional capacitance or resistance associated with the width bias value, for at least one of the first polygon and the second polygon. In this way, RC extraction, during a design phase, can take into account electrical characteristic changes that occur during fabrication.

Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract: The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.

Abstract: A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other.

Abstract: A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector value is calculated based, at least in part, on a plurality of criteria vectors of the benchmark circuits. A shift is applied on each of the groups by the tuning vector value and a technology file, such as a 2.5 dimensional RC techfile, is regenerated.

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.

Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.

Abstract: The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.

Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.