Patents by Inventor Ke-Ying Su
Ke-Ying Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8572537Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: GrantFiled: June 19, 2012Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan-Sin Chang, Chien-Wen Chen
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Publication number: 20130275927Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.Type: ApplicationFiled: May 23, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8495532Abstract: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.Type: GrantFiled: March 31, 2011Date of Patent: July 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Publication number: 20130174112Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.Type: ApplicationFiled: February 10, 2012Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming HO, Ke-Ying SU, Hsiao-Shu CHAO, Yi-Kan CHENG
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Publication number: 20130139121Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.Type: ApplicationFiled: February 6, 2012Publication date: May 30, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ze-Ming Wu, Ching-Shun Yang, Ke-Ying Su, Hsiao-Shu Chao
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Patent number: 8453095Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.Type: GrantFiled: July 6, 2011Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8418112Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.Type: GrantFiled: March 3, 2011Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou
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Publication number: 20130014070Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.Type: ApplicationFiled: July 6, 2011Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying SU, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8336002Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.Type: GrantFiled: March 20, 2007Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gwan Sin Chang, Yi-Kan Cheng, Ivy Chiu, Ke-Ying Su
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Publication number: 20120260225Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: ApplicationFiled: June 19, 2012Publication date: October 11, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
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Publication number: 20120254811Abstract: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ke-Ying SU, Ching-Shun YANG, Jui-Feng KUAN, Hsiao-Shu CHAO, Yi-Kan CHENG
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Publication number: 20120226479Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou
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Patent number: 8252489Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.Type: GrantFiled: June 24, 2011Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8214784Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: GrantFiled: September 29, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
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Publication number: 20120052422Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen, Ru-Gun Liu, Wen-Chun Huang
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Publication number: 20120054696Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.Type: ApplicationFiled: June 24, 2011Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8119310Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.Type: GrantFiled: August 31, 2010Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen, Ru-Gun Liu, Wen-Chun Huang
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Publication number: 20110023003Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: ApplicationFiled: September 29, 2010Publication date: January 27, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
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Patent number: 7818698Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: GrantFiled: October 1, 2007Date of Patent: October 19, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
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Publication number: 20090007035Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.Type: ApplicationFiled: October 1, 2007Publication date: January 1, 2009Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen