Patents by Inventor Kedar Satish Chitnis
Kedar Satish Chitnis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326002Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.Type: ApplicationFiled: June 12, 2023Publication date: October 12, 2023Inventors: Mihir Narendra MODY, JR., Veeramanikandan RAJU, Niraj NANDAN, Samuel Paul VISALLI, Jason A.T. JONES, Kedar Satish CHITNIS, Gregory Raymond SHURTZ, Prithvi Shankar YEYYADI ANANTHA, Sriramakrishnan GOVINDARAJAN
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Publication number: 20230267084Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Inventors: Mihir Narendra MODY, JR., Ankur ANKUR, Vivek Vilas DHANDE, Kedar Satish CHITNIS, Niraj NANDAN, Brijesh JADAV, Shyam JAGANNATHAN, Prithvi Shankar YEYYADI ANANTHA, Santhanakrishnan Narayanan NARAYANAN
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Publication number: 20230244557Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Inventors: Kedar Satish Chitnis, Charles Lance Fuoco, Sriramakrishnan Govindarajan, Mihir Narendra Mody, William A. Mills, Gregory Raymond Shurtz, Amritpal Singh Mundra
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Patent number: 11715188Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.Type: GrantFiled: February 28, 2022Date of Patent: August 1, 2023Assignee: Texas Instruments IncorporatedInventors: Mihir Narendra Mody, Veeramanikandan Raju, Niraj Nandan, Samuel Paul Visalli, Jason A. T. Jones, Kedar Satish Chitnis, Gregory Raymond Shurtz, Prithvi Shankar Yeyyadi Anantha, Sriramakrishnan Govindarajan
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Patent number: 11681534Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.Type: GrantFiled: March 23, 2021Date of Patent: June 20, 2023Assignee: Texas Instruments IncorporatedInventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
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Publication number: 20230185904Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventors: Kedar Satish CHITNIS, Mihir Narendra MODY, Amritpal Singh MUNDRA, Yashwant DUTT, Gregory Raymond SHURTZ, Robert John TIVY
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Patent number: 11656925Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: GrantFiled: December 30, 2020Date of Patent: May 23, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kedar Satish Chitnis, Charles Lance Fuoco, Sriramakrishnan Govindarajan, Mihir Narendra Mody, William A. Mills, Gregory Raymond Shurtz, Amritpal Singh Mundra
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Publication number: 20230013998Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.Type: ApplicationFiled: July 19, 2021Publication date: January 19, 2023Inventors: Mihir Narendra MODY, Kedar Satish CHITNIS, Kumar DESAPPAN, David SMITH, Pramod Kumar SWAMI, Shyam JAGANNATHAN
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Publication number: 20220391776Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run a ML model, receiving synchronization information for organizing the running of the ML model with other ML models, determining, based on the synchronization information, to delay running the ML model, delaying the running of the ML model, determining, based on the synchronization information, a time to run the ML model; and running the ML model at the time.Type: ApplicationFiled: June 8, 2021Publication date: December 8, 2022Inventors: Mihir Narendra MODY, Kumar DESAPPAN, Kedar Satish CHITNIS, Pramod Kumar SWAMI, Kevin Patrick LAVERY, Prithvi Shankar YEYYADI ANANTHA, Shyam JAGANNATHAN
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Publication number: 20210232406Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.Type: ApplicationFiled: March 23, 2021Publication date: July 29, 2021Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
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Publication number: 20210117254Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Inventors: Kedar Satish Chitnis, Charles Lance Fuoco, Sriramakrishnan Govindarajan, Mihir Narendra Mody, William A. Mills, Gregory Raymond Shurtz, Amritpal Singh Mundra
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Publication number: 20210103465Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedType: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Inventors: Hetul Sanghvi, Niraj Nandan, Mihir Narendra Mody, Kedar Satish Chitnis
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Patent number: 10956169Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.Type: GrantFiled: March 31, 2016Date of Patent: March 23, 2021Assignee: Texas Instruments IncorporatedInventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
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Patent number: 10929209Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: GrantFiled: April 8, 2019Date of Patent: February 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kedar Satish Chitnis, Charles Lance Fuoco, Sriramakrishnan Govindarajan, Mihir Narendra Mody, William A. Mills, Gregory Raymond Shurtz, Amritpal Singh Mundra
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Patent number: 10908946Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.Type: GrantFiled: December 30, 2016Date of Patent: February 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hetul Sanghvi, Niraj Nandan, Mihir Narendra Mody, Kedar Satish Chitnis
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Publication number: 20200210256Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: ApplicationFiled: April 8, 2019Publication date: July 2, 2020Inventors: Kedar Satish CHITNIS, Charles Lance FUOCO, Sriramakrishnan GOVINDARAJAN, Mihir Narendra MODY, William A. MILLS, Gregory Raymond SHURTZ, Amritpal Singh MUNDRA
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Patent number: 10489206Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.Type: GrantFiled: December 30, 2016Date of Patent: November 26, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hetul Sanghvi, Niraj Nandan, Mihir Narendra Mody, Kedar Satish Chitnis
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Publication number: 20180189105Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Hetul Sanghvi, Niraj Nandan, Mihir Narendra Mody, Kedar Satish Chitnis
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Publication number: 20180189102Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Hetul Sanghvi, Niraj Nandan, Mihir Narendra Mody, Kedar Satish Chitnis
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Publication number: 20170123810Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.Type: ApplicationFiled: March 31, 2016Publication date: May 4, 2017Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg