Patents by Inventor Kee-Jeung Lee

Kee-Jeung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110171808
    Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jae-Sung ROH, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
  • Publication number: 20110169134
    Abstract: A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park
  • Publication number: 20110128668
    Abstract: An electrode of a semiconductor device includes a TiCN layer and a TiN layer. A method for fabricating an electrode of a semiconductor device includes preparing a substrate, forming a TiCN layer, and forming a TiN layer.
    Type: Application
    Filed: June 28, 2010
    Publication date: June 2, 2011
    Inventors: Kwan-Woo DO, Kee-Jeung Lee, Kyung-Woong Park, Jeong-Yeop Lee
  • Publication number: 20110128667
    Abstract: In a semiconductor device including a carbon-containing electrode and a method for fabricating the same, an electrode has a high work function due to a carbon-containing TiN layer contained therein. It is possible to provide a dielectric layer having a high permittivity and thus to reduce the leakage current by forming an electrode having a high work function. Also, sufficient capacitance of a capacitor can be secured by employing an electrode having a high work function and a dielectric layer having a high permittivity.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 2, 2011
    Inventors: Kwan-Woo Do, Kee-Jeung Lee, Young-Dae Kim, Mi-Hyoung Lee, Jeong-Yeop Lee
  • Publication number: 20110073925
    Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.
    Type: Application
    Filed: December 30, 2009
    Publication date: March 31, 2011
    Inventors: Eun-Shil PARK, Young-Seok Eun, Kee-Jeung Lee, Min-Soo Kim
  • Patent number: 7910428
    Abstract: A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park
  • Patent number: 7910452
    Abstract: A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial layer is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer and the sacrificial layer are then removed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
  • Patent number: 7858483
    Abstract: A method for forming a capacitor of a semiconductor device includes forming a first insulation layer having a storage node plug on a semiconductor substrate; forming an etch stop layer and a second insulation layer sequentially on the substrate having the first insulation layer; forming a hole exposing a portion of the storage node plug by selectively etching the second insulation layer by using the etch stop layer; recessing a portion of the storage node plug exposed by the hole; forming a barrier metal layer on a surface of the recessed storage node plug; forming a storage node electrode connected to the storage node plug through the barrier metal layer in the hole; and forming a dielectric layer and a metal layer for a plate electrode sequentially on the storage node electrode.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Bok Choi, Jong Bum Park, Kee Jeung Lee, Jong Min Lee
  • Publication number: 20100276804
    Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
    Type: Application
    Filed: July 16, 2010
    Publication date: November 4, 2010
    Inventors: Jin-Hyock KIM, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
  • Patent number: 7825043
    Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-Jeung Lee
  • Patent number: 7816202
    Abstract: A method for fabricating a capacitor includes providing a substrate having a capacitor region is employed, forming a first Ru1?xOx layer over the substrate, forming a Ru layer for a lower electrode over the first Ru1?xOx layer and deoxidizing the first Ru1?xOx layer, forming a dielectric layer over the Ru layer for a lower electrode, and forming a conductive layer for an upper electrode over the dielectric layer, wherein the first Ru1?xOx layer contains oxygen in an amount less than an oxygen amount of a RuO2 layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: October 19, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Woo Do, Jae-Sung Roh, Kee-Jeung Lee, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kyung-Woong Park
  • Patent number: 7781336
    Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jin-Hyock Kim, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
  • Publication number: 20100096609
    Abstract: A phase change memory device that has a layered phase change layer composed of multiple phase change materials is presented. The device includes a semiconductor substrate, an interlayer dielectric layer, a high-temperature crystallization phase change, a low-temperature crystallization phase change layer, and an upper electrode. The interlayer dielectric layer formed on the semiconductor substrate and the high-temperature crystallization phase change layer is formed on the interlayer dielectric layer. The low-temperature crystallization phase change layer is formed over the high-temperature crystallization phase change layer. The upper electrode is formed over the low-temperature crystallization phase change layer. An optional diffusion barrier may be interposed between the two phase change layers.
    Type: Application
    Filed: June 29, 2009
    Publication date: April 22, 2010
    Inventors: Jin Hyock KIM, Kee Jeung LEE, Deok Sin KIL
  • Publication number: 20100084740
    Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 8, 2010
    Inventor: Kee-Jeung Lee
  • Patent number: 7670903
    Abstract: A method for fabricating a cylindrical capacitor. The method includes forming an isolation structure including an interlayer on a substrate, the substrate having a plurality of contact plugs formed therein, forming a plurality of opening regions by etching the isolation structure, thereby exposing selected portions of the contact plugs, forming storage nodes on a surface of the opening regions, etching selected portions of the isolation structure to form a patterned interlayer that encompasses selected portions of the storage nodes, thereby supporting the storage nodes, removing remaining portions of the isolation structure, and removing the patterned interlayer to expose inner and outer walls of the storage nodes.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Ki-Seon Park, Jae-Sung Roh, Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Jin-Hyock Kim, Kee-Jeung Lee
  • Publication number: 20100047989
    Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 25, 2010
    Inventor: Kee-jeung Lee
  • Publication number: 20100046138
    Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.
    Type: Application
    Filed: December 24, 2008
    Publication date: February 25, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kwan-Woo DO, Kee-Jeung LEE, Deok-Sin KIL, Young-Dae KIM, Jin-Hyock KIM, Kyung-Woong PARK, Jeong-Yeop LEE
  • Publication number: 20100012989
    Abstract: A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes.
    Type: Application
    Filed: December 30, 2008
    Publication date: January 21, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kee-Jeung LEE, Jae-Sung ROH, Deok-Sin KIL, Young-Dae KIM, Jin-Hyock KIM, Kwan-Woo DO, Kyung-Woong PARK, Jeong-Yeop LEE
  • Publication number: 20090273882
    Abstract: A capacitor includes a first electrode, a dielectric layer, and a second electrode. The capacitor also includes a buffer layer formed over at least one of an interface between the first electrode and the dielectric layer and an interface between the dielectric layer and the second electrode, wherein the buffer layer includes a compound of a metal element from electrode materials of one of the first and second electrodes and a metal element from materials included in the dielectric layer.
    Type: Application
    Filed: April 21, 2009
    Publication date: November 5, 2009
    Inventors: Kyung-Woong PARK, Kee-Jeung LEE, Deok-Sin KIL, Young-Dae KIM, Jin-Hyock KIM, Kwan-Woo DO, Jeong-Yeop LEE
  • Patent number: 7608517
    Abstract: Disclosed is a method for forming a capacitor of a semiconductor device, which can secure wanted charging capacity and also improve leakage current characteristics. The method comprises the steps of: forming a storage electrode on a semiconductor substrate; forming a dielectric layer formed of Ti(1-x)TbxO on the storage electrode; and forming a plate electrode on the dielectric layer formed of Ti(1-x)TbxO.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: October 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee Jeung Lee