Patents by Inventor Kee-Jeung Lee

Kee-Jeung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090261454
    Abstract: A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuXTiYOZ film is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation of a bottom electrode, a dielectric layer and a top electrode over a substrate includes forming a RuXTiYOZ film during a formation of at least one of the bottom electrode and top electrode, where x, y and z are positive real numbers.
    Type: Application
    Filed: December 23, 2008
    Publication date: October 22, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kwan-Woo DO, Kee-Jeung LEE, Deok-Sin KIL, Young-Dae KIM, Jin-Hyock KIM, Kyung-Woong PARK, Jeong-Yeop LEE
  • Publication number: 20090263967
    Abstract: A noble metal layer is formed using ozone (O3) as a reaction gas.
    Type: Application
    Filed: December 30, 2008
    Publication date: October 22, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Deok-Sin Kil, Kee-Jeung Lee, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park, Jeong-Yeop Lee, Ja-Yong Kim
  • Patent number: 7592217
    Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: September 22, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-jeung Lee
  • Patent number: 7531422
    Abstract: The present invention relates to a method for fabricating a capacitor in a semiconductor device through the use of hafnium-terbium oxide (Hf1-xTbxO) as a dielectric layer. The method includes the steps of: forming a lower electrode on a substrate; forming an amorphous hafnium-terbium oxide (Hf1-xTbxO) dielectric layer on the lower electrode; crystallizing the Hf1-xTbxO dielectric layer by performing a thermal process; and forming an upper electrode on the Hf1-xTbxO dielectric layer.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: May 12, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung Lee, Jae-Sung Roh
  • Publication number: 20090061587
    Abstract: A method for fabricating a capacitor includes providing a substrate having a capacitor region is employed, forming a first Ru1-xOx layer over the substrate, forming a Ru layer for a lower electrode over the first Ru1-xOx layer and deoxidizing the first Ru1-xOx layer, forming a dielectric layer over the Ru layer for a lower electrode, and forming a conductive layer for an upper electrode over the dielectric layer, wherein the first Ru1-xOx layer contains oxygen in an amount less than an oxygen amount of a RuO2 layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: March 5, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kwan-Woo Do, Jae-Sung Roh, Kee-Jeung Lee, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kyung-Woong Park
  • Patent number: 7499259
    Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: March 3, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-Jeung Lee
  • Publication number: 20090008743
    Abstract: A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer.
    Type: Application
    Filed: June 29, 2008
    Publication date: January 8, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park
  • Publication number: 20090002917
    Abstract: A capacitor includes a lower electrode, a dielectric layer over the lower electrode, and an upper electrode having a stack structure including a ruthenium-containing layer and a tungsten-containing layer over the dielectric layer.
    Type: Application
    Filed: December 28, 2007
    Publication date: January 1, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Deok-Sin KIL, Kee-Jeung Lee, Han-Sang Song, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park
  • Publication number: 20090004808
    Abstract: A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters.
    Type: Application
    Filed: December 27, 2007
    Publication date: January 1, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung LEE, Jae-Sung Roh, Seung-Jin Yeom, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do
  • Publication number: 20080272490
    Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
    Type: Application
    Filed: October 30, 2007
    Publication date: November 6, 2008
    Inventors: Jin-Hyock Kim, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
  • Publication number: 20080157278
    Abstract: A capacitor includes a lower electrode, a dielectric layer, an upper electrode, and a ruthenium oxide layer. At least one of the lower electrode and the upper electrode is formed of a ruthenium layer, and the ruthenium oxide layer is disposed next to the ruthenium layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kwan-Woo Do, Jae-Sung Roh, Kee-Jeung Lee, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kyung-Woong Park, Han-Sang Song
  • Publication number: 20080089004
    Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.
    Type: Application
    Filed: December 4, 2007
    Publication date: April 17, 2008
    Inventor: Kee-Jeung Lee
  • Publication number: 20080081431
    Abstract: A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial layer is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer and the sacrificial layer are then removed.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jae-Sung ROH, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
  • Patent number: 7320943
    Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 22, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-Jeung Lee
  • Publication number: 20080003741
    Abstract: A method for fabricating a cylindrical capacitor. The method includes forming an isolation structure including an interlayer on a substrate, the substrate having a plurality of contact plugs formed therein, forming a plurality of opening regions by etching the isolation structure, thereby exposing selected portions of the contact plugs, forming storage nodes on a surface of the opening regions, etching selected portions of the isolation structure to form a patterned interlayer that encompasses selected portions of the storage nodes, thereby supporting the storage nodes, removing remaining portions of the isolation structure, and removing the patterned interlayer to expose inner and outer walls of the storage nodes.
    Type: Application
    Filed: December 28, 2006
    Publication date: January 3, 2008
    Inventors: Ki-Seon Park, Jae-Sung Roh, Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Jin-Hyock Kim, Kee-Jeung Lee
  • Patent number: 7273781
    Abstract: To form a capacitor in a semiconductor device, an etching barrier layer and a mold insulating layer are sequentially formed on an interlayer insulating film having a contact plug. A hole exposing the contact plug is formed by etching the mold insulating layer and the etching barrier layer. A first blocking layer having a wet etching rate lower than that of the mold insulating layer is formed on the hole sidewall. A storage electrode and a second blocking layer made from the identical material of the first blocking layer are formed on the resultant structure. The predetermined portions of the second blocking layer and the metal layer formed on the mold insulating layer are removed. A cylinder type storage electrode is formed by wet etching the mold insulating layer. A dielectric layer is formed on the cylinder type storage electrode. A plate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: September 25, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee Jeung Lee
  • Publication number: 20070122967
    Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.
    Type: Application
    Filed: June 28, 2006
    Publication date: May 31, 2007
    Applicant: Hynix Semiconductor, Inc.
    Inventor: Kee-Jeung Lee
  • Publication number: 20070117309
    Abstract: The present invention relates to a method for fabricating a capacitor in a semiconductor device through the use of hafnium-terbium oxide (Hf1-xTbxO) as a dielectric layer. The method includes the steps of: forming a lower electrode on a substrate; forming an amorphous hafnium-terbium oxide (Hf1-xTbxO) dielectric layer on the lower electrode; crystallizing the Hf1-xTbxO dielectric layer by performing a thermal process; and forming an upper electrode on the Hf1-xTbxO dielectric layer.
    Type: Application
    Filed: January 11, 2007
    Publication date: May 24, 2007
    Inventors: Kee-Jeung Lee, Jae-Sung Roh
  • Patent number: 7199004
    Abstract: Disclosed is a method of forming a capacitor of a semiconductor device which can secure a desired leakage current characteristic while securing a desired charging capacitance. The inventive method of forming a capacitor of a semiconductor device comprises steps of: forming a bottom electrode on a semiconductor substrate with a storage node contact so that the bottom electrode is connected with the storage node contact; plasma-nitrifying the bottom electrode to form a first nitrification film on the surface of the bottom electrode; forming a LaTbO dielectric film on the bottom electrode including the first nitrification film; plasma-nitrifying the LaTbO dielectric film to form a second nitrification film on the surface of the LaTbO dielectric film; and forming a top electrode on the LaTbO dielectric film including the second nitrification film.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 3, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee Jeung Lee
  • Publication number: 20070042540
    Abstract: To form a capacitor in a semiconductor device, an etching barrier layer and a mold insulating layer are sequentially formed on an interlayer insulating film having a contact plug. A hole exposing the contact plug is formed by etching the mold insulating layer and the etching barrier layer. A first blocking layer having a wet etching rate lower than that of the mold insulating layer is formed on the hole sidewall. A storage electrode and a second blocking layer made from the identical material of the first blocking layer are formed on the resultant structure. The predetermined portions of the second blocking layer and the metal layer formed on the mold insulating layer are removed. A cylinder type storage electrode is formed by wet etching the mold insulating layer. A dielectric layer is formed on the cylinder type storage electrode. A plate electrode is formed on the dielectric layer.
    Type: Application
    Filed: October 20, 2005
    Publication date: February 22, 2007
    Inventor: Kee Jeung Lee