Abstract: Disclosed herein is a semiconductor device including: a first middle-voltage element disposed in a substrate and configured to receive a first level middle-voltage; a second middle-voltage element disposed in the substrate and configured to receive a second level middle-voltage greater than the first level middle-voltage; and a deep well disposed in the substrate so as to surround the first middle-voltage element and the second middle-voltage element, wherein the second middle-voltage element includes: a second-first middle-voltage well doped with a first type dopant; and a second-second middle-voltage well doped with a second type dopant different from the first type dopant.

Abstract: Disclosed herein is a driver integrated circuit (IC), which can be miniaturized and includes a plurality of circuits, including a first substrate, a first circuit driven at a first level voltage and mounted on the first substrate, a second substrate bonded to the first substrate, and a second circuit including one or more sub-circuits driven at a second level voltage that is higher than the first level voltage, wherein at least one among the one or more sub-circuits is mounted on the second substrate.

Abstract: Disclosed herein is a driver integrated circuit (IC), which can be miniaturized and includes a plurality of circuits, including a first substrate, a first circuit driven at a first level voltage and mounted on the first substrate, a second substrate bonded to the first substrate, and a second circuit including one or more sub-circuits driven at a second level voltage that is higher than the first level voltage, wherein at least one among the one or more sub-circuits is mounted on the second substrate.

Abstract: Disclosed herein is a driver integrated circuit (IC), which can be miniaturized and includes a plurality of circuits, including a first substrate, a first circuit driven at a first level voltage and mounted on the first substrate, a second substrate bonded to the first substrate, and a second circuit including one or more sub-circuits driven at a second level voltage that is higher than the first level voltage, wherein at least one among the one or more sub-circuits is mounted on the second substrate.

Abstract: The present disclosure provides a light-emitting display device including a first substrate and a second substrate, a first circuit layer provided on one surface of the first substrate, a second circuit layer provided on one surface of the second substrate facing the first substrate, a first pad layer provided on one surface of the first circuit layer, a second pad layer provided on one surface of the second circuit layer and electrically connected to the first pad layer, and a light-emitting element layer provided on the other surface of the second substrate that does not face the first substrate, and a method of manufacturing the same.

Abstract: Disclosed is a Schottky barrier diode which may be applied to an application that requires a low off current (Ioff), such as a mobile integrated circuit. The Schottky barrier diode can improve a blocking characteristic for a backward current flow while maintaining an advantage of a turn-on current, by improving the structure of a contact surface that is pinched off by depletion.

Abstract: Disclosed herein is a driver integrated circuit (IC), which can be miniaturized and includes a plurality of circuits, including a first substrate, a first circuit driven at a first level voltage and mounted on the first substrate, a second substrate bonded to the first substrate, and a second circuit including one or more sub-circuits driven at a second level voltage that is higher than the first level voltage, wherein at least one among the one or more sub-circuits is mounted on the second substrate.

Abstract: Disclosed is a Schottky barrier diode which may be applied to an application that requires a low off current (Ioff), such as a mobile integrated circuit. The Schottky barrier diode can improve a blocking characteristic for a backward current flow while maintaining an advantage of a turn-on current, by improving the structure of a contact surface that is pinched off by depletion.

Abstract: A voltage generator configured to generate a plurality of voltage groups, each of the plurality of voltage groups including a plurality of reference voltages, and a decoder having an output node configured to output one of the plurality of reference voltages is disclosed. The decoder includes switch blocks that correspond to the plurality of voltage groups. Each of the switch blocks includes transistors that are turned on or off by or in response to a control signal, and each transistor in one of the switch blocks has a channel width different from a channel width of each transistor in another one of the switch blocks.

Abstract: A DEMOS transistor includes a semiconductor substrate defining a field region and an active region, a gate pattern disposed on the semiconductor substrate, the gate pattern being positioned over both the active region and the field region, drift regions disposed in the active region and positioned adjacent to both sides of the gate pattern, high concentration ion regions disposed in the drift regions, and being spaced apart from the gate pattern, and a silicide blocking layer having a exposure hole exposing one of an upper surface of the gate pattern and the high concentration ion regions, the silicide blocking layer having a ring shape to at least partially surround one of the upper surface of the gate pattern and the high concentration ion regions.

Abstract: A voltage generator configured to generate a plurality of voltage groups, each of the plurality of voltage groups including a plurality of reference voltages, and a decoder having an output node configured to output one of the plurality of reference voltages is disclosed. The decoder includes switch blocks that correspond to the plurality of voltage groups. Each of the switch blocks includes transistors that are turned on or off by or in response to a control signal, and each transistor in one of the switch blocks has a channel width different from a channel width of each transistor in another one of the switch blocks.

Abstract: A high voltage semiconductor device includes a gate electrode structure disposed on a substrate, a source region disposed in the substrate to be adjacent to one side of the gate electrode structure, a first drift region disposed in the substrate to be adjacent to another side of the gate electrode structure, a drain region electrically connected with the first drift region, and a device isolation region disposed on one side of the drain region. Particularly, the first drift region is spaced apart from the device isolation region.

Abstract: A high voltage semiconductor device includes a gate electrode structure disposed on a substrate, a source region disposed in the substrate to be adjacent to one side of the gate electrode structure, a first drift region disposed in the substrate to be adjacent to another side of the gate electrode structure, a drain region electrically connected with the first drift region, and a device isolation region disposed on one side of the drain region. Particularly, the first drift region is spaced apart from the device isolation region.

Abstract: Disclosed is a semiconductor package. The semiconductor package includes a substrate formed with transistors, power metal lines formed on the substrate, data metal lines formed on the substrate to transmit and receive data to and from the transistors, and an insulating layer formed on the substrate, the power metal lines, and the data metal lines. Herein, the insulating layer has openings partially exposing the power metal lines.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes: forming a photoresist pattern having a first opening over a substrate; forming a first impurity region inside the substrate exposed to the first opening; partially etching the photoresist pattern by a plasma ashing process using oxygen (O2) gas to form a second opening having a width broader than that of the first opening; and forming a second impurity region inside the substrate exposed through the second opening, wherein the width of the second opening varies according to a plasma ashing time.

Abstract: There is provided a semiconductor device. The semiconductor device includes a lower electrode, a contact connected to the lower electrode to have a double trench structure, a phase change material layer accommodated in the double trench to cause a phase change between a crystalline state and an amorphous state in accordance with a change in heat transmitted by the contact, and an upper electrode connected to the phase change material layer.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes: forming a photoresist pattern having a first opening over a substrate; forming a first impurity region inside the substrate exposed to the first opening; partially etching the photoresist pattern by a plasma ashing process using oxygen (O2) gas to form a second opening having a width broader than that of the first opening; and forming a second impurity region inside the substrate exposed through the second opening, wherein the width of the second opening varies according to a plasma ashing time.

Abstract: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

Abstract: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

Abstract: A method is provided for manufacturing a semiconductor device. The method may be capable of simplifying the formation of wells by reducing the number of process steps. In the method for manufacturing a semiconductor device including a high voltage device and a low voltage device, a P-well is formed simultaneously with a P-drift region, and an N-well is formed simultaneously with an N-drift region, so that the wells and drift regions are formed in one process, thereby reducing the manufacturing cost and time, and improving the yield rate.