Patents by Inventor Kee-Sang KWON
Kee-Sang KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10847416Abstract: A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.Type: GrantFiled: October 31, 2018Date of Patent: November 24, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun Hee Bai, Sung Woo Kang, Kee Sang Kwon, Dong Seok Lee, Sang Hyun Lee, Jeong Yun Lee, Yong-Ho Jeon
-
Patent number: 10734380Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: GrantFiled: October 12, 2018Date of Patent: August 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
-
Patent number: 10714472Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: GrantFiled: August 14, 2017Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
-
Patent number: 10446561Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: GrantFiled: August 29, 2018Date of Patent: October 15, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
-
Patent number: 10438891Abstract: An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.Type: GrantFiled: September 7, 2017Date of Patent: October 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-jine Park, Kee-sang Kwon, Jae-jik Baek, Yong-sun Ko, Kwang-wook Lee
-
Publication number: 20190295889Abstract: A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.Type: ApplicationFiled: October 31, 2018Publication date: September 26, 2019Inventors: Keun Hee BAI, Sung Woo KANG, Kee Sang KWON, Dong Seok LEE, Sang Hyun LEE, Jeong Yun LEE, Yong-Ho JEON
-
Patent number: 10297474Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.Type: GrantFiled: February 19, 2014Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Won-Sang Choi
-
Publication number: 20190043860Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: ApplicationFiled: October 12, 2018Publication date: February 7, 2019Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
-
Publication number: 20180374859Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: ApplicationFiled: August 29, 2018Publication date: December 27, 2018Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
-
Patent number: 10128236Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: GrantFiled: January 27, 2016Date of Patent: November 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
-
Patent number: 10115797Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.Type: GrantFiled: March 3, 2016Date of Patent: October 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yeol Song, Wan-don Kim, Sang-Jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
-
Patent number: 10096605Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: GrantFiled: August 18, 2017Date of Patent: October 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
-
Publication number: 20180254246Abstract: An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.Type: ApplicationFiled: September 7, 2017Publication date: September 6, 2018Inventors: Sang-jine PARK, Kee-sang KWON, Jae-jik BAEK, Yong-sun KO, Kwang-wook LEE
-
Publication number: 20180197861Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.Type: ApplicationFiled: March 9, 2018Publication date: July 12, 2018Inventors: Sang Jine Park, KI HYUNG KO, KEE SANG KWON, JAE JIK BAEK, BO UN YOON, YONG SUN KO
-
Patent number: 9960241Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.Type: GrantFiled: January 6, 2016Date of Patent: May 1, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjine Park, Kee Sang Kwon, Jae-Jik Baek, Boun Yoon
-
Patent number: 9947672Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: GrantFiled: December 7, 2016Date of Patent: April 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
-
Publication number: 20170345822Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Inventors: Kee Sang Kwon, Boun YOON, Sangjine PARK, Myunggeun SONG, Ki-Hyung KO, Jiwon YUN
-
Publication number: 20170345825Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: ApplicationFiled: August 18, 2017Publication date: November 30, 2017Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
-
Patent number: 9755079Abstract: Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.Type: GrantFiled: January 19, 2016Date of Patent: September 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Keun-Hee Bai, Kyoung-Hwan Yeo, Bo-Un Yoon, Kee-Sang Kwon, Do-Hyoung Kim, Ha-Young Jeon, Seung-Seok Ha
-
Patent number: 9754880Abstract: The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.Type: GrantFiled: February 5, 2016Date of Patent: September 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jik Baek, Kee-Sang Kwon, Sang-Jine Park, Bo-Un Yoon