Patents by Inventor Kee-Sang KWON

Kee-Sang KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190295889
    Abstract: A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.
    Type: Application
    Filed: October 31, 2018
    Publication date: September 26, 2019
    Inventors: Keun Hee BAI, Sung Woo KANG, Kee Sang KWON, Dong Seok LEE, Sang Hyun LEE, Jeong Yun LEE, Yong-Ho JEON
  • Publication number: 20190043860
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 7, 2019
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Publication number: 20180374859
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Application
    Filed: August 29, 2018
    Publication date: December 27, 2018
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10128236
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Patent number: 10115797
    Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Sang-Jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
  • Patent number: 10096605
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Publication number: 20180254246
    Abstract: An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 6, 2018
    Inventors: Sang-jine PARK, Kee-sang KWON, Jae-jik BAEK, Yong-sun KO, Kwang-wook LEE
  • Publication number: 20180197861
    Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Sang Jine Park, KI HYUNG KO, KEE SANG KWON, JAE JIK BAEK, BO UN YOON, YONG SUN KO
  • Patent number: 9960241
    Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangjine Park, Kee Sang Kwon, Jae-Jik Baek, Boun Yoon
  • Patent number: 9947672
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: April 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Publication number: 20170345825
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Publication number: 20170345822
    Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventors: Kee Sang Kwon, Boun YOON, Sangjine PARK, Myunggeun SONG, Ki-Hyung KO, Jiwon YUN
  • Patent number: 9754880
    Abstract: The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jik Baek, Kee-Sang Kwon, Sang-Jine Park, Bo-Un Yoon
  • Patent number: 9755079
    Abstract: Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Keun-Hee Bai, Kyoung-Hwan Yeo, Bo-Un Yoon, Kee-Sang Kwon, Do-Hyoung Kim, Ha-Young Jeon, Seung-Seok Ha
  • Patent number: 9748234
    Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: August 29, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
  • Publication number: 20170084617
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Application
    Filed: December 7, 2016
    Publication date: March 23, 2017
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 9548309
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Publication number: 20160351570
    Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.
    Type: Application
    Filed: May 10, 2016
    Publication date: December 1, 2016
    Inventors: Sang Jine Park, Kl HYUNG KO, KEE SANG KWON, JAE JIK BAEK, BO UN YOON, YONG SUN KO
  • Publication number: 20160315045
    Abstract: The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.
    Type: Application
    Filed: February 5, 2016
    Publication date: October 27, 2016
    Inventors: Jae-Jik BAEK, Kee-Sang KWON, Sang-Jine PARK, Bo-Un YOON
  • Publication number: 20160308012
    Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 20, 2016
    Inventors: Jae-yeol Song, Wan-don Kim, Sang-jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung