Patents by Inventor Kee-Sang KWON
Kee-Sang KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9748234Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: GrantFiled: August 14, 2015Date of Patent: August 29, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
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Publication number: 20170084617Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: ApplicationFiled: December 7, 2016Publication date: March 23, 2017Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
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Patent number: 9548309Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: GrantFiled: February 18, 2016Date of Patent: January 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
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Publication number: 20160351570Abstract: A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded sources/drains can each include an upper surface having a recessed portion and an outer raised portion relative to the recessed portion. A second conductivity type finFET device can include second embedded sources/drains of a second material that have a second etch rate than is greater that the first etch rate. The second embedded sources/drains can each include an upper surface that is at a different level than the outer raised portions of the first conductivity type finFET device.Type: ApplicationFiled: May 10, 2016Publication date: December 1, 2016Inventors: Sang Jine Park, Kl HYUNG KO, KEE SANG KWON, JAE JIK BAEK, BO UN YOON, YONG SUN KO
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Publication number: 20160315045Abstract: The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.Type: ApplicationFiled: February 5, 2016Publication date: October 27, 2016Inventors: Jae-Jik BAEK, Kee-Sang KWON, Sang-Jine PARK, Bo-Un YOON
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Publication number: 20160308012Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.Type: ApplicationFiled: March 3, 2016Publication date: October 20, 2016Inventors: Jae-yeol Song, Wan-don Kim, Sang-jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
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Publication number: 20160284806Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region n the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.Type: ApplicationFiled: January 6, 2016Publication date: September 29, 2016Inventors: Sangjine Park, Kee Sang Kwon, Jae-Jik Baek, Boun Yoon
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Publication number: 20160284699Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.Type: ApplicationFiled: January 27, 2016Publication date: September 29, 2016Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
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Publication number: 20160268414Abstract: Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.Type: ApplicationFiled: January 19, 2016Publication date: September 15, 2016Inventors: Sang-Jine PARK, Keun-Hee BAI, Kyoung-Hwan YEO, Bo-Un YOON, Kee-Sang KWON, Do-Hyoung KIM, Ha-Young JEON, Seung-Seok HA
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Publication number: 20160163718Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
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Patent number: 9299700Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: GrantFiled: March 5, 2015Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
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Publication number: 20160064378Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.Type: ApplicationFiled: August 14, 2015Publication date: March 3, 2016Inventors: Kee Sang KWON, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
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Publication number: 20150325575Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.Type: ApplicationFiled: March 5, 2015Publication date: November 12, 2015Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
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Patent number: 9117692Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.Type: GrantFiled: October 14, 2014Date of Patent: August 25, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangjine Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wonsang Choi
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Patent number: 9054210Abstract: A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.Type: GrantFiled: May 24, 2012Date of Patent: June 9, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Jine Park, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han, Kee-Sang Kwon, Won-Sang Choi
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Patent number: 9040415Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.Type: GrantFiled: May 23, 2014Date of Patent: May 26, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Byung-Kwon Cho, Ji-Hoon Cha
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Publication number: 20150050793Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.Type: ApplicationFiled: May 23, 2014Publication date: February 19, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Jine PARK, Bo-Un YOON, Young-Sang YOUN, Jeong-Nam HAN, Kee-Sang KWON, Doo-Sung YUN, Byung-Kwon CHO, Ji-Hoon CHA
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Publication number: 20150028423Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Inventors: Sangjine Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wonsang Choi
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Patent number: 8889552Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.Type: GrantFiled: November 19, 2013Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sangline Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wongsang Choi
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Patent number: 8841769Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.Type: GrantFiled: March 12, 2013Date of Patent: September 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjine Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Wonsang Choi